From 01db217ab927dd1f415f28d6ac726edb73ae2ee0 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Mon, 6 May 2019 16:23:43 +0200 Subject: [PATCH] Add supervisor support in the ExternalInterruptArrayPlugin --- .../scala/vexriscv/plugin/CsrPlugin.scala | 2 +- .../plugin/ExternalInterruptArrayPlugin.scala | 21 +++++++++++++------ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 3c7b036..467dc76 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -310,7 +310,7 @@ trait IContextSwitching{ def isContextSwitching : Bool } -class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface{ +class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface{ import config._ import CsrAccess._ diff --git a/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala b/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala index fd1a561..43d32f0 100644 --- a/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala +++ b/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala @@ -3,7 +3,11 @@ package vexriscv.plugin import spinal.core._ import vexriscv.VexRiscv -class ExternalInterruptArrayPlugin(arrayWidth : Int = 32, maskCsrId : Int = 0xBC0, pendingsCsrId : Int = 0xFC0) extends Plugin[VexRiscv]{ +class ExternalInterruptArrayPlugin(arrayWidth : Int = 32, + machineMaskCsrId : Int = 0xBC0, + machinePendingsCsrId : Int = 0xFC0, + supervisorMaskCsrId : Int = 0x9C0, + supervisorPendingsCsrId : Int = 0xDC0) extends Plugin[VexRiscv]{ var externalInterruptArray : Bits = null override def setup(pipeline: VexRiscv): Unit = { @@ -12,10 +16,15 @@ class ExternalInterruptArrayPlugin(arrayWidth : Int = 32, maskCsrId : Int = 0xBC override def build(pipeline: VexRiscv): Unit = { val csr = pipeline.service(classOf[CsrPlugin]) - val mask = Reg(Bits(arrayWidth bits)) init(0) - val pendings = mask & RegNext(externalInterruptArray) - csr.externalInterrupt.setAsDirectionLess() := pendings.orR - csr.rw(maskCsrId, mask) - csr.r(pendingsCsrId, pendings) + val externalInterruptArrayBuffer = RegNext(externalInterruptArray) + def gen(maskCsrId : Int, pendingsCsrId : Int, interruptPin : Bool) = new Area { + val mask = Reg(Bits(arrayWidth bits)) init(0) + val pendings = mask & externalInterruptArrayBuffer + interruptPin.setAsDirectionLess() := pendings.orR + csr.rw(maskCsrId, mask) + csr.r(pendingsCsrId, pendings) + } + gen(machineMaskCsrId, machinePendingsCsrId, csr.externalInterrupt) + if(csr.config.supervisorGen) gen(supervisorMaskCsrId, supervisorPendingsCsrId, csr.externalInterruptS) } }