From 01e5112680cd437cca7151bd13bf220fc85e1ec9 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Sun, 23 Feb 2020 10:44:44 +0100 Subject: [PATCH] Fetcher RVC ensure redo keep PC(1) Fix BranchTarget RVC inibition --- src/main/scala/vexriscv/plugin/Fetcher.scala | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala index 4b76336..4200982 100644 --- a/src/main/scala/vexriscv/plugin/Fetcher.scala +++ b/src/main/scala/vexriscv/plugin/Fetcher.scala @@ -247,7 +247,6 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, val bufferValid = RegInit(False) val bufferData = Reg(Bits(16 bits)) - val isInputLowRvc = input.rsp.inst(1 downto 0) =/= 3 val isInputHighRvc = input.rsp.inst(17 downto 16) =/= 3 val throw2BytesReg = RegInit(False) @@ -283,6 +282,10 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, throw2BytesReg := False bufferValid := False } + + if(fetchPc.redo != null) { + fetchPc.redo.payload(1) setWhen(throw2BytesReg) + } }) @@ -576,7 +579,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, } //Do not trigger prediction hit when it is one for the upper RVC word and we aren't there yet - decompressorContextOutput.hit clearWhen(decompressorContext.line.last2Bytes && !decompressor.throw2Bytes) + decompressorContextOutput.hit clearWhen(decompressorContext.line.last2Bytes && (decompressor.bufferValid || (!decompressor.throw2Bytes && decompressor.isInputLowRvc))) decodePc.predictionPcLoad.valid := injectorContext.line.branchWish.msb && injectorContext.hit && !injectorContext.hazard && injector.decodeInput.fire decodePc.predictionPcLoad.payload := injectorContext.line.target