From 04ca72df66c6b828619490b4099fe4e349f96cb3 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Tue, 5 Dec 2017 16:29:26 +0100
Subject: [PATCH] Update README.md

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 8421fe3..21641e8 100644
--- a/README.md
+++ b/README.md
@@ -44,7 +44,7 @@ The hardware description of this CPU is done by using an very software oriented
 
 The following number where obtains by synthesis the CPU as toplevel without any specific synthesis option to save area or to get better maximal frequency (neutral).<br>
 The clock constraint is set to a unattainable value, which tends to increase the design area.<br>
-
+The dhrystone benchmark were compiled with -O3 -fno-inline<br>
 The used CPU corresponding configuration can be find in src/scala/vexriscv/demo.
 
 ```