diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
index 479b982..24d94af 100644
--- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
@@ -1697,6 +1697,13 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
               csrMapping.allowCsrSignal := True
             }
           }
+          //When no HPM
+          if(!csrMapping.mapping.contains(0xB03)){
+            val masked = U(csrAddress & 0xF60)
+            when(arbitration.isValid && input(IS_CSR) && U(csrAddress(4 downto 0)) >= 3 && (masked === 0xB00 || masked === 0xC00 && !writeInstruction && privilege === 3 || U(csrAddress & 0xFE0) === 0x320)){
+              csrMapping.allowCsrSignal := True
+            }
+          }
 
           illegalAccess clearWhen(csrMapping.allowCsrSignal)