diff --git a/src/main/scala/vexriscv/plugin/Plugin.scala b/src/main/scala/vexriscv/plugin/Plugin.scala
index 957a12e..96d2bc6 100644
--- a/src/main/scala/vexriscv/plugin/Plugin.scala
+++ b/src/main/scala/vexriscv/plugin/Plugin.scala
@@ -10,7 +10,10 @@ trait Plugin[T <: Pipeline] extends Nameable{
   var pipeline : T = null.asInstanceOf[T]
   setName(this.getClass.getSimpleName.replace("$",""))
 
+  // Used to setup things with other plugins
   def setup(pipeline: T) : Unit = {}
+
+  //Used to flush out the required hardware (called after setup)
   def build(pipeline: T) : Unit
 
   implicit class implicitsStage(stage: Stage){
diff --git a/src/test/scala/vexriscv/ip/fpu/FpuTest.scala b/src/test/scala/vexriscv/ip/fpu/FpuTest.scala
index 290e39b..fb5943a 100644
--- a/src/test/scala/vexriscv/ip/fpu/FpuTest.scala
+++ b/src/test/scala/vexriscv/ip/fpu/FpuTest.scala
@@ -68,7 +68,6 @@ class FpuTest extends FunSuite{
       dut.clockDomain.forkSimSpeedPrinter(5.0)
 
 
-
       class TestCase(op : String){
         def build(arg : String) = new ProcessStream(s"testfloat_gen $arg -tininessafter -forever -$op"){
           def f32_f32_f32 ={