From 0f17b395bd3d86772f22530ee8930c45a45d29f5 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Thu, 2 Nov 2023 11:59:33 +0100
Subject: [PATCH] IBusDBusCachedTightlyCoupledRam add missing write mask

---
 src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
index e32ff96..6f85652 100644
--- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -680,7 +680,8 @@ class IBusDBusCachedTightlyCoupledRam(mapping : SizeMapping, withIBus : Boolean
           address = (dbus.address >> 2).resized,
           data    = dbus.write_data,
           enable  = dbus.enable,
-          write   = dbus.write_enable
+          write   = dbus.write_enable,
+          mask    = dbus.write_mask
         )
       }
       val i = withIBus generate new Area {