From 08189ee9073d84e6d7c0df2d3e4cbbaa3d632191 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Tue, 2 Jun 2020 19:13:55 +0200
Subject: [PATCH] DebugPlugin now support Bmb

---
 .../scala/vexriscv/plugin/DebugPlugin.scala   | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
index 91185b8..9f2a243 100644
--- a/src/main/scala/vexriscv/plugin/DebugPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
@@ -9,6 +9,8 @@ import spinal.core._
 import spinal.lib._
 import spinal.lib.bus.amba3.apb.{Apb3, Apb3Config}
 import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
+import spinal.lib.bus.bmb.{Bmb, BmbAccessParameter, BmbParameter}
+import spinal.lib.bus.simple.PipelinedMemoryBus
 
 import scala.collection.mutable.ArrayBuffer
 
@@ -22,6 +24,16 @@ case class DebugExtensionRsp() extends Bundle{
   val data = Bits(32 bit)
 }
 
+object DebugExtensionBus{
+  def getBmbAccessParameter(source : BmbAccessParameter) = BmbAccessParameter(
+    addressWidth = 8,
+    dataWidth    = 32,
+    lengthWidth  = 2,
+    sourceWidth  = source.sourceWidth,
+    contextWidth = source.contextWidth
+  )
+}
+
 case class DebugExtensionBus() extends Bundle with IMasterSlave{
   val cmd = Stream(DebugExtensionCmd())
   val rsp = DebugExtensionRsp() //one cycle latency
@@ -63,6 +75,41 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
     bus
   }
 
+  def fromPipelinedMemoryBus(): PipelinedMemoryBus ={
+    val bus = PipelinedMemoryBus(32, 32)
+
+    cmd.arbitrationFrom(bus.cmd)
+    cmd.wr := bus.cmd.write
+    cmd.address := bus.cmd.address.resized
+    cmd.data := bus.cmd.data
+
+    bus.rsp.valid := RegNext(cmd.fire) init(False)
+    bus.rsp.data := rsp.data
+
+    bus
+  }
+
+  def fromBmb(): Bmb ={
+    val bus = Bmb(BmbParameter(
+      addressWidth  = 8,
+      dataWidth     = 32,
+      lengthWidth   = 2,
+      sourceWidth   = 0,
+      contextWidth  = 0
+    ))
+
+    cmd.arbitrationFrom(bus.cmd)
+    cmd.wr := bus.cmd.isWrite
+    cmd.address := bus.cmd.address
+    cmd.data := bus.cmd.data
+
+    bus.rsp.valid := RegNext(cmd.fire) init(False)
+    bus.rsp.data := rsp.data
+    bus.rsp.last := True
+
+    bus
+  }
+
   def from(c : SystemDebuggerConfig) : SystemDebuggerMemBus = {
     val mem = SystemDebuggerMemBus(c)
     cmd.valid          := mem.cmd.valid