From 09ac23b78f708c752017ab4ca59e001234c513e2 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 1 May 2020 12:45:16 +0200 Subject: [PATCH] Fix SMP fence lock when 4 stages CPU --- src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index 1d5adbb..17c429c 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -314,7 +314,7 @@ class DBusCachedPlugin(val config : DataCacheConfig, } when(arbitration.isValid && (input(MEMORY_FENCE) || aquire)){ - memory.arbitration.haltByOther := True //Ensure that the fence affect the memory stage instruction by stoping it + mmuAndBufferStage.arbitration.haltByOther := True //Ensure that the fence affect the memory stage instruction by stoping it } }