From 0aa6e0573d6f69bacbe6006ea801944e19175b88 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 16 Jan 2023 12:43:01 +0100 Subject: [PATCH] shorter satp export --- src/main/scala/vexriscv/plugin/MmuPlugin.scala | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/MmuPlugin.scala b/src/main/scala/vexriscv/plugin/MmuPlugin.scala index 423b1ce..f8bd88f 100644 --- a/src/main/scala/vexriscv/plugin/MmuPlugin.scala +++ b/src/main/scala/vexriscv/plugin/MmuPlugin.scala @@ -93,18 +93,12 @@ class MmuPlugin(ioRange : UInt => Bool, val sum, mxr, mprv = RegInit(False) mprv clearWhen(csrService.xretAwayFromMachine) } - val satp = if(exportSatp) { - new Area { - val mode = out(RegInit(False)) - val asid = out(Reg(Bits(9 bits))) - // Bottom 20 bits are used in implementation, but top 2 bits are still stored for OS use. - val ppn = out(Reg(UInt(22 bits))) - } - } else { - new Area { - val mode = RegInit(False) - val asid = Reg(Bits(9 bits)) - val ppn = Reg(UInt(22 bits)) + val satp = new Area { + val mode = RegInit(False) + val asid = Reg(Bits(9 bits)) + val ppn = Reg(UInt(22 bits)) // Bottom 20 bits are used in implementation, but top 2 bits are still stored for OS use. + if(exportSatp) { + out(mode, asid, ppn) } }