From 0ada869b2d5d623423fa7cb809d3b3fc1a35b87e Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 1 Oct 2018 16:14:21 +0200 Subject: [PATCH] regression golden ref regfile is now sync with trl boot's random values wip --- src/main/scala/vexriscv/demo/GenFull.scala | 2 +- src/main/scala/vexriscv/demo/GenFullNoMmu.scala | 2 +- .../scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala | 2 +- .../scala/vexriscv/demo/GenFullNoMmuNoCache.scala | 2 +- .../vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala | 2 +- .../vexriscv/demo/GenSmallAndPerformant.scala | 2 +- .../demo/GenSmallAndPerformantICache.scala | 2 +- src/main/scala/vexriscv/demo/GenSmallest.scala | 2 +- .../scala/vexriscv/demo/GenSmallestNoCsr.scala | 2 +- src/main/scala/vexriscv/demo/SynthesisBench.scala | 14 ++++++++++---- .../scala/vexriscv/demo/VexRiscvAvalonForSim.scala | 2 +- .../demo/VexRiscvAvalonWithIntegratedJtag.scala | 2 +- .../demo/VexRiscvCachedWishboneForSim.scala | 2 +- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 2 +- .../scala/vexriscv/plugin/DBusSimplePlugin.scala | 2 +- src/test/cpp/regression/main.cpp | 5 +++++ 16 files changed, 29 insertions(+), 18 deletions(-) diff --git a/src/main/scala/vexriscv/demo/GenFull.scala b/src/main/scala/vexriscv/demo/GenFull.scala index 36b0b4d..5f45df2 100644 --- a/src/main/scala/vexriscv/demo/GenFull.scala +++ b/src/main/scala/vexriscv/demo/GenFull.scala @@ -63,7 +63,7 @@ object GenFull extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenFullNoMmu.scala b/src/main/scala/vexriscv/demo/GenFullNoMmu.scala index 62c8e58..e1aa722 100644 --- a/src/main/scala/vexriscv/demo/GenFullNoMmu.scala +++ b/src/main/scala/vexriscv/demo/GenFullNoMmu.scala @@ -55,7 +55,7 @@ object GenFullNoMmu extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala b/src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala index 7a4d2b0..e675aa0 100644 --- a/src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala +++ b/src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala @@ -56,7 +56,7 @@ object GenFullNoMmuMaxPerf extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala b/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala index 24cb45c..b110a9d 100644 --- a/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala +++ b/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala @@ -28,7 +28,7 @@ object GenFullNoMmuNoCache extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala b/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala index c63efe6..32bf99f 100644 --- a/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala +++ b/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala @@ -33,7 +33,7 @@ object GenNoCacheNoMmuMaxPerf extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala b/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala index d5a2f77..f38ca85 100644 --- a/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala +++ b/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala @@ -28,7 +28,7 @@ object GenSmallAndProductive extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala b/src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala index b6eb53f..29d179d 100644 --- a/src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala +++ b/src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala @@ -42,7 +42,7 @@ object GenSmallAndProductiveICache extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenSmallest.scala b/src/main/scala/vexriscv/demo/GenSmallest.scala index bd5b78f..1626ddb 100644 --- a/src/main/scala/vexriscv/demo/GenSmallest.scala +++ b/src/main/scala/vexriscv/demo/GenSmallest.scala @@ -28,7 +28,7 @@ object GenSmallest extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala b/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala index f8f571e..a1e9455 100644 --- a/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala +++ b/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala @@ -33,7 +33,7 @@ object GenSmallestNoCsr extends App{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true, + zeroBoot = false, writeRfInMemoryStage = false ), new IntAluPlugin, diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala index 07f22fb..31a929c 100644 --- a/src/main/scala/vexriscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -101,8 +101,8 @@ object VexRiscvSynthesisBench { } -// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) - val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache) + val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) +// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache) // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) // val rtls = List(smallestNoCsr) @@ -113,8 +113,14 @@ object VexRiscvSynthesisBench { quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin" ) ++ IcestormStdTargets().take(1) -// val targets = IcestormStdTargets() - Bench(rtls, targets, "/eda/tmp/") +// val targets = AlteraStdTargets( +// quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", +// quartusCycloneVPath = null +// ) + + + // val targets = IcestormStdTargets() + Bench(rtls, targets, "/eda/tmp") } } diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala index fb872aa..e1adf95 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala @@ -82,7 +82,7 @@ object VexRiscvAvalonForSim{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala index ebaabba..6ec2fd9 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala @@ -80,7 +80,7 @@ object VexRiscvAvalonWithIntegratedJtag{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala index 20254b6..ebf5e82 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala @@ -79,7 +79,7 @@ object VexRiscvCachedWishboneForSim{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = true + zeroBoot = false ), new IntAluPlugin, new SrcPlugin( diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index e047a20..afa9b24 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -735,7 +735,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio execute plug new Area { import execute._ def previousStage = decode - val blockedBySideEffects = List(memory, writeBack).map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR + val blockedBySideEffects = List(memory, writeBack).map(s => s.arbitration.isValid).orR // && s.input(HAS_SIDE_EFFECT) to improve be less pessimistic val illegalAccess = arbitration.isValid && input(IS_CSR) val illegalInstruction = False diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index f86fcc6..9ef683b 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -182,7 +182,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ } -class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, catchAccessFault : Boolean = false, earlyInjection : Boolean = false) extends Plugin[VexRiscv]{ +class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, catchAccessFault : Boolean = false, earlyInjection : Boolean = false/*, idempotentRegions : (UInt) => Bool = (x) => False*/) extends Plugin[VexRiscv]{ var dBus : DBusSimpleBus = null diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 40478de..721c588 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -718,6 +718,11 @@ public: logTraces.open (name + ".logTrace"); fillSimELements(); clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &start_time); + + //Sync register file initial content + for(int i = 1;i < 32;i++){ + riscvRef.regs[i] = top->VexRiscv->RegFilePlugin_regFile[i]; + } } virtual ~Workspace(){