diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala
index 3464165..4d2b2a2 100644
--- a/src/main/scala/vexriscv/ip/DataCache.scala
+++ b/src/main/scala/vexriscv/ip/DataCache.scala
@@ -567,7 +567,7 @@ class DataCache(val p : DataCacheConfig) extends Component{
     val consistancyCheck = (withInvalidate || withWriteResponse) generate new Area {
       val fenceConsistent =  (if(withInvalidate) sync.fenceConsistent else pending.done) && !io.cpu.writeBack.fenceValid && !io.cpu.memory.fenceValid //Pessimistic fence tracking
       val totalyConsistent = (if(withInvalidate) sync.totalyConsistent else pending.done) && !(io.cpu.memory.isValid && io.cpu.memory.isWrite) && !(io.cpu.writeBack.isValid && io.cpu.memory.isWrite)
-      when(io.cpu.execute.isValid && (!io.cpu.execute.args.wr || isAmo)){
+      when(io.cpu.execute.isValid /*&& (!io.cpu.execute.args.wr || isAmo)*/){
         when(!fenceConsistent || io.cpu.execute.totalyConsistent && !totalyConsistent){
           io.cpu.execute.haltIt := True
         }
diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
index 8308bc0..12f38f3 100644
--- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -236,7 +236,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
             if(withLrSc) insert(MEMORY_FENCE_BACK) setWhen(input(MEMORY_LRSC))
             if(withAmo)  insert(MEMORY_FENCE_BACK) setWhen(input(MEMORY_AMO))
           }
-          when(input(INSTRUCTION)(25)) { //RL but a bit pessimistic as it could be MEMORY_FENCE_BACK when the memory op isn't a read
+          when(input(INSTRUCTION)(25)) { //RL
             if(withLrSc) insert(MEMORY_FENCE_FRONT) setWhen(input(MEMORY_LRSC))
             if(withAmo)  insert(MEMORY_FENCE_FRONT) setWhen(input(MEMORY_AMO))
           }