From 0d39e38906d7ac9b5e07d81814c6fe48fb8e7f34 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 28 Dec 2017 13:49:20 +0100 Subject: [PATCH] SpinalHDL 1.1.0 --- build.sbt | 4 ++-- src/test/scala/vexriscv/MuraxSim.scala | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/build.sbt b/build.sbt index 391df58..375a21c 100644 --- a/build.sbt +++ b/build.sbt @@ -9,8 +9,8 @@ scalaVersion := "2.11.6" EclipseKeys.withSource := true libraryDependencies ++= Seq( - "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.5", - "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.5", + "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.1.0", + "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.1.0", "org.yaml" % "snakeyaml" % "1.8" ) diff --git a/src/test/scala/vexriscv/MuraxSim.scala b/src/test/scala/vexriscv/MuraxSim.scala index 0c02d04..2ea608f 100644 --- a/src/test/scala/vexriscv/MuraxSim.scala +++ b/src/test/scala/vexriscv/MuraxSim.scala @@ -17,7 +17,7 @@ object MuraxSim { // def config = MuraxConfig.default.copy(onChipRamSize = 256 kB) def config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex") - SimConfig(new Murax(config)).allOptimisation.doManagedSim{dut => + SimConfig.allOptimisation.compile(new Murax(config)).doSim{dut => val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong val jtagClkPeriod = mainClkPeriod*4 val uartBaudRate = 115200