From 10d282b2ef393f1cebef7b91da68106c989a2392 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Wed, 26 Jul 2017 23:36:25 +0200 Subject: [PATCH] Add DBusSimple early injection feature (better DMIPS) --- src/main/scala/vexriscv/TestsWorkspace.scala | 3 ++- .../scala/vexriscv/plugin/DBusSimplePlugin.scala | 12 +++++++----- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index acc5e2f..cd020e1 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -58,7 +58,8 @@ object TestsWorkspace { ), // new DBusSimplePlugin( // catchAddressMisaligned = true, -// catchAccessFault = true +// catchAccessFault = true, +// earlyInjection = false // ), new DBusCachedPlugin( config = new DataCacheConfig( diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index 713d554..e1214e0 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -133,7 +133,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ } -class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Boolean) extends Plugin[VexRiscv]{ +class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Boolean, earlyInjection : Boolean = false) extends Plugin[VexRiscv]{ var dBus : DBusSimpleBus = null @@ -161,7 +161,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool SRC2_CTRL -> Src2CtrlEnum.IMI, REGFILE_WRITE_VALID -> True, BYPASSABLE_EXECUTE_STAGE -> False, - BYPASSABLE_MEMORY_STAGE -> False + BYPASSABLE_MEMORY_STAGE -> Bool(earlyInjection) ) val storeActions = stdActions ++ List( @@ -249,8 +249,9 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool } //Reformat read responses, REGFILE_WRITE_DATA overriding - writeBack plug new Area { - import writeBack._ + val injectionStage = if(earlyInjection) memory else writeBack + injectionStage plug new Area { + import injectionStage._ val rspShifted = MEMORY_READ_DATA() @@ -271,7 +272,8 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool input(REGFILE_WRITE_DATA) := rspFormated } - assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(INSTRUCTION)(5) && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend") + if(!earlyInjection) + assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(INSTRUCTION)(5) && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend") } } }