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VexRiscv
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Exposed write mask on default iBus

This commit is contained in:
MrJake222 2024-06-04 23:11:10 +02:00
parent 457ae5c7e5
commit 1175f195df
1 changed files with 2 additions and 0 deletions
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2
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
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@ -16,6 +16,7 @@ import scala.collection.mutable.ArrayBuffer
case class DBusSimpleCmd() extends Bundle{ case class DBusSimpleCmd() extends Bundle{
val wr = Bool val wr = Bool
val mask = Bits(4 bit)
val address = UInt(32 bits) val address = UInt(32 bits)
val data = Bits(32 bit) val data = Bits(32 bit)
val size = UInt(2 bit) val size = UInt(2 bit)
@ -441,6 +442,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
//formal //formal
val formalMask = dBus.genMask(dBus.cmd) val formalMask = dBus.genMask(dBus.cmd)
dBus.cmd.mask := formalMask
insert(FORMAL_MEM_ADDR) := dBus.cmd.address & U"xFFFFFFFC" insert(FORMAL_MEM_ADDR) := dBus.cmd.address & U"xFFFFFFFC"
insert(FORMAL_MEM_WMASK) := (dBus.cmd.valid && dBus.cmd.wr) ? formalMask | B"0000" insert(FORMAL_MEM_WMASK) := (dBus.cmd.valid && dBus.cmd.wr) ? formalMask | B"0000"