From 1179c6551f41e0a4c293fa29da6417bc51984e86 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Wed, 8 Mar 2023 16:00:22 +0800 Subject: [PATCH] Fix #321 #322 #333 FPU precision removal --- src/main/scala/vexriscv/ip/fpu/FpuCore.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/scala/vexriscv/ip/fpu/FpuCore.scala b/src/main/scala/vexriscv/ip/fpu/FpuCore.scala index 9cdaab5..d9dcf69 100644 --- a/src/main/scala/vexriscv/ip/fpu/FpuCore.scala +++ b/src/main/scala/vexriscv/ip/fpu/FpuCore.scala @@ -1546,7 +1546,7 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{ val manAggregate = input.value.mantissa @@ input.scrap val expBase = muxDouble[UInt](input.format)(exponentF64Subnormal + 1)(exponentF32Subnormal + 1) val expDif = expBase -^ input.value.exponent - val expSubnormal = !expDif.msb + val expSubnormal = !input.value.special && !expDif.msb var discardCount = (expSubnormal ? expDif.resize(log2Up(p.internalMantissaSize) bits) | U(0)) if (p.withDouble) when(input.format === FpuFormat.FLOAT) { discardCount \= discardCount + 29 @@ -1577,10 +1577,11 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{ val adderMantissa = input.value.mantissa(mantissaRange) & (mantissaIncrement ? ~(exactMask.trim(1) >> 1) | input.value.mantissa(mantissaRange).maxValue) val adderRightOp = (mantissaIncrement ? (exactMask >> 1)| U(0)).resize(p.internalMantissaSize bits) val adder = KeepAttribute(KeepAttribute(input.value.exponent @@ adderMantissa) + KeepAttribute(adderRightOp) + KeepAttribute(U(mantissaIncrement))) + val masked = adder & ~((exactMask >> 1).resize(p.internalMantissaSize).resize(widthOf(adder))) math.special := input.value.special math.sign := input.value.sign - math.exponent := adder(p.internalMantissaSize, p.internalExponentSize bits) - math.mantissa := adder(0, p.internalMantissaSize bits) + math.exponent := masked(p.internalMantissaSize, p.internalExponentSize bits) + math.mantissa := masked(0, p.internalMantissaSize bits) val patched = CombInit(math) val nx,of,uf = False