From 11cc9b1cf277df10886d8a6cae46e4a073a99154 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 2 Nov 2023 12:31:05 +0100 Subject: [PATCH] Add GenFullWithTcmIntegrated example --- README.md | 2 +- .../demo/GenFullWithTcmIntegrated.scala | 97 +++++++++++++++++++ 2 files changed, 98 insertions(+), 1 deletion(-) create mode 100644 src/main/scala/vexriscv/demo/GenFullWithTcmIntegrated.scala diff --git a/README.md b/README.md index 30c814e..165341f 100644 --- a/README.md +++ b/README.md @@ -72,7 +72,7 @@ This repository hosts a RISC-V implementation written in SpinalHDL. Here are som - Linux compatible (SoC : https://github.com/enjoy-digital/linux-on-litex-vexriscv) - Zephyr compatible - [FreeRTOS port](https://github.com/Dolu1990/FreeRTOS-RISCV) -- Support tightly coupled memory on I$ D$ (see GenFullWithTcm) +- Support tightly coupled memory on I$ D$ (see GenFullWithTcm / GenFullWithTcmIntegrated) The hardware description of this CPU is done by using a very software oriented approach (without any overhead in the generated hardware). Here is a list of software concepts used: diff --git a/src/main/scala/vexriscv/demo/GenFullWithTcmIntegrated.scala b/src/main/scala/vexriscv/demo/GenFullWithTcmIntegrated.scala new file mode 100644 index 0000000..4e68b5f --- /dev/null +++ b/src/main/scala/vexriscv/demo/GenFullWithTcmIntegrated.scala @@ -0,0 +1,97 @@ +package vexriscv.demo + +import spinal.core._ +import spinal.lib.bus.misc.SizeMapping +import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} +import vexriscv.plugin._ +import vexriscv.{VexRiscv, VexRiscvConfig, plugin} + +/** + * this example integrate the tightly coupled memory directly inside VexRiscv + * by using the IBusDBusCachedTightlyCoupledRam plugin + */ +object GenFullWithTcmIntegrated extends App{ + def config = VexRiscvConfig( + plugins = List( + new IBusDBusCachedTightlyCoupledRam( + mapping = SizeMapping(0x20000000, 0x1000) + ), + new IBusCachedPlugin( + prediction = DYNAMIC, + config = InstructionCacheConfig( + cacheSize = 4096, + bytePerLine =32, + wayCount = 1, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchIllegalAccess = true, + catchAccessFault = true, + asyncTagMemory = false, + twoCycleRam = true, + twoCycleCache = true + ), + memoryTranslatorPortConfig = MmuPortConfig( + portTlbSize = 4 + ) + ), + new DBusCachedPlugin( + config = new DataCacheConfig( + cacheSize = 4096, + bytePerLine = 32, + wayCount = 1, + addressWidth = 32, + cpuDataWidth = 32, + memDataWidth = 32, + catchAccessError = true, + catchIllegal = true, + catchUnaligned = true + ), + memoryTranslatorPortConfig = MmuPortConfig( + portTlbSize = 6 + ) + ), + new MmuPlugin( + virtualRange = _(31 downto 28) === 0xC, + ioRange = _(31 downto 28) === 0xF + ), + new DecoderSimplePlugin( + catchIllegalInstruction = true + ), + new RegFilePlugin( + regFileReadyKind = plugin.SYNC, + zeroBoot = false + ), + new IntAluPlugin, + new SrcPlugin( + separatedAddSub = false, + executeInsertion = true + ), + new FullBarrelShifterPlugin, + new HazardSimplePlugin( + bypassExecute = true, + bypassMemory = true, + bypassWriteBack = true, + bypassWriteBackBuffer = true, + pessimisticUseSrc = false, + pessimisticWriteRegFile = false, + pessimisticAddressMatch = false + ), + new MulPlugin, + new DivPlugin, + new CsrPlugin(CsrPluginConfig.small(0x80000020l)), + new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), + new BranchPlugin( + earlyBranch = false, + catchAddressMisaligned = true + ), + new YamlPlugin("cpu0.yaml") + ) + ) + + def cpu() = new VexRiscv( + config + ) + + SpinalVerilog(cpu()) +}