From 12463e40a46079167d226b56ed1969b3b43e117a Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Tue, 3 Mar 2020 15:59:30 +0100
Subject: [PATCH] improve debugPlugin step logic

---
 src/main/scala/vexriscv/plugin/DebugPlugin.scala | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
index a1051d7..8c990f9 100644
--- a/src/main/scala/vexriscv/plugin/DebugPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
@@ -213,11 +213,14 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount :
         iBusFetcher.haltIt()
       }
 
-      when(stepIt && iBusFetcher.incoming()) {
-        iBusFetcher.haltIt()
+      when(stepIt) {
+        //Assume nothing will stop the CPU in the decode stage
         when(decode.arbitration.isValid) {
           haltIt := True
         }
+        when(execute.arbitration.isValid) {
+          decode.arbitration.flushNext := True
+        }
       }
 
       //Avoid having two C instruction executed in a single step