From 12d21a08e81a01e5227841590e3f6c80f56d7448 Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Fri, 14 Jul 2017 19:28:22 +0200
Subject: [PATCH] Add DebugPlugin avalon

---
 .../scala/VexRiscv/Plugin/DebugPlugin.scala   | 19 +++++++++++++++++--
 src/main/scala/VexRiscv/demo/Briey.scala      |  2 +-
 .../scala/VexRiscv/demo/VexRiscvAvalon.scala  |  4 ++++
 3 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/VexRiscv/Plugin/DebugPlugin.scala b/src/main/scala/VexRiscv/Plugin/DebugPlugin.scala
index 90b42ea..0ae5db9 100644
--- a/src/main/scala/VexRiscv/Plugin/DebugPlugin.scala
+++ b/src/main/scala/VexRiscv/Plugin/DebugPlugin.scala
@@ -6,6 +6,7 @@ import VexRiscv.ip._
 import spinal.core._
 import spinal.lib._
 import spinal.lib.bus.amba3.apb.{Apb3Config, Apb3}
+import spinal.lib.bus.avalon.{AvalonMMConfig, AvalonMM}
 
 
 case class DebugExtensionCmd() extends Bundle{
@@ -19,14 +20,14 @@ case class DebugExtensionRsp() extends Bundle{
 
 case class DebugExtensionBus() extends Bundle with IMasterSlave{
   val cmd = Stream(DebugExtensionCmd())
-  val rsp = DebugExtensionRsp() //One cycle latency
+  val rsp = DebugExtensionRsp() //zero cycle latency
 
   override def asMaster(): Unit = {
     master(cmd)
     in(rsp)
   }
 
-  def toApb3(): Apb3 ={
+  def fromApb3(): Apb3 ={
     val apb = Apb3(Apb3Config(
       addressWidth = 8,
       dataWidth = 32,
@@ -43,6 +44,20 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
 
     apb
   }
+
+  def fromAvalon(): AvalonMM ={
+    val bus = AvalonMM(AvalonMMConfig.fixed(addressWidth = 8,dataWidth = 32, readLatency = 0))
+
+    cmd.valid := bus.read || bus.write
+    cmd.wr := bus.write
+    cmd.address := bus.address
+    cmd.data := bus.writeData
+
+    bus.waitRequestn := cmd.ready
+    bus.readData := rsp.data
+
+    bus
+  }
 }
 
 case class DebugExtensionIo() extends Bundle with IMasterSlave{
diff --git a/src/main/scala/VexRiscv/demo/Briey.scala b/src/main/scala/VexRiscv/demo/Briey.scala
index 83e7a85..37f3559 100644
--- a/src/main/scala/VexRiscv/demo/Briey.scala
+++ b/src/main/scala/VexRiscv/demo/Briey.scala
@@ -304,7 +304,7 @@ class Briey(config: BrieyConfig) extends Component{
         }
         case plugin : DebugPlugin      => {
           resetCtrl.coreResetUnbuffered setWhen(plugin.io.resetOut)
-          debugBus = plugin.io.bus.toApb3()
+          debugBus = plugin.io.bus.fromApb3()
         }
         case _ =>
       }
diff --git a/src/main/scala/VexRiscv/demo/VexRiscvAvalon.scala b/src/main/scala/VexRiscv/demo/VexRiscvAvalon.scala
index 0603174..f6a0dd3 100644
--- a/src/main/scala/VexRiscv/demo/VexRiscvAvalon.scala
+++ b/src/main/scala/VexRiscv/demo/VexRiscvAvalon.scala
@@ -132,6 +132,10 @@ object VexRiscvAvalon{
             plugin.dBus.asDirectionLess()
             master(plugin.dBus.toAvalon()).setName("dBusAvalon")
           }
+          case plugin: DebugPlugin => {
+            plugin.io.bus.asDirectionLess()
+            slave(plugin.io.bus.fromAvalon()).setName("debugBusAvalon")
+          }
           case _ =>
         }
       }