From 1303c0ca7c42db16f7bf65ba17b82caf2e284bc4 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 9 Jun 2022 17:57:24 +0200 Subject: [PATCH] CfuPlugin.withEnable added --- src/main/scala/vexriscv/plugin/CfuPlugin.scala | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CfuPlugin.scala b/src/main/scala/vexriscv/plugin/CfuPlugin.scala index 9a93f6c..d343640 100644 --- a/src/main/scala/vexriscv/plugin/CfuPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CfuPlugin.scala @@ -101,7 +101,8 @@ class CfuPlugin(val stageCount : Int, val busParameter : CfuBusParameter, val encodings : List[CfuPluginEncoding] = null, val stateAndIndexCsrOffset : Int = 0xBC0, - val statusCsrOffset : Int = 0x801) extends Plugin[VexRiscv]{ + val statusCsrOffset : Int = 0x801, + val withEnable : Boolean = true) extends Plugin[VexRiscv]{ def p = busParameter assert(p.CFU_INPUTS <= 2) @@ -158,8 +159,8 @@ class CfuPlugin(val stageCount : Int, val csr = pipeline plug new Area{ val factory = pipeline.service(classOf[CsrInterface]) - val en = Reg(Bool()) init(False) - factory.rw(stateAndIndexCsrOffset, 31, en) + val en = withEnable generate (Reg(Bool()) init(False)) + if(withEnable) factory.rw(stateAndIndexCsrOffset, 31, en) val stateId = Reg(UInt(log2Up(p.CFU_STATE_INDEX_NUM) bits)) init(0) if(p.CFU_STATE_INDEX_NUM > 1) { @@ -181,7 +182,7 @@ class CfuPlugin(val stageCount : Int, } } - when(decode.input(CFU_ENABLE) && !csr.en){ + if(withEnable) when(decode.input(CFU_ENABLE) && !csr.en){ pipeline.service(classOf[DecoderService]).forceIllegal() }