diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala index 6caac47..d70a71a 100644 --- a/src/main/scala/vexriscv/plugin/Fetcher.scala +++ b/src/main/scala/vexriscv/plugin/Fetcher.scala @@ -20,7 +20,8 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, val injectorReadyCutGen : Boolean, val prediction : BranchPrediction, val historyRamSizeLog2 : Int, - val injectorStage : Boolean) extends Plugin[VexRiscv] with JumpService with IBusFetcher{ + val injectorStage : Boolean, + val relaxPredictorAddress : Boolean) extends Plugin[VexRiscv] with JumpService with IBusFetcher{ var prefetchExceptionPort : Flow[ExceptionCause] = null var decodePrediction : DecodePredictionBus = null var fetchPrediction : FetchPredictionBus = null @@ -498,6 +499,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, predictionJumpInterface.valid := decodePrediction.cmd.hadBranch && decode.arbitration.isFiring //TODO OH Doublon de priorité predictionJumpInterface.payload := decode.input(PC) + ((decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL) ? imm.j_sext | imm.b_sext).asUInt + if(relaxPredictorAddress) KeepAttribute(predictionJumpInterface.payload) // when(predictionJumpInterface.payload((if(pipeline(RVC_GEN)) 0 else 1) downto 0) =/= 0){ // decodePrediction.cmd.hadBranch := False diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala index 03285f0..d2fffc6 100644 --- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala @@ -34,7 +34,8 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, config : InstructionCacheConfig, memoryTranslatorPortConfig : Any = null, injectorStage : Boolean = false, - withoutInjectorStage : Boolean = false) extends IBusFetcherImpl( + withoutInjectorStage : Boolean = false, + relaxPredictorAddress : Boolean = true) extends IBusFetcherImpl( resetVector = resetVector, keepPcPlus4 = keepPcPlus4, decodePcGen = compressedGen, @@ -44,7 +45,8 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, injectorReadyCutGen = false, prediction = prediction, historyRamSizeLog2 = historyRamSizeLog2, - injectorStage = (!config.twoCycleCache && !withoutInjectorStage) || injectorStage){ + injectorStage = (!config.twoCycleCache && !withoutInjectorStage) || injectorStage, + relaxPredictorAddress = relaxPredictorAddress){ import config._ assert(!(withoutInjectorStage && injectorStage)) diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index 5d6ad0b..8f0c909 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -172,7 +172,8 @@ class IBusSimplePlugin(resetVector : BigInt, pendingMax : Int = 7, injectorStage : Boolean = true, rspHoldValue : Boolean = false, - singleInstructionPipeline : Boolean = false + singleInstructionPipeline : Boolean = false, + relaxPredictorAddress : Boolean = true ) extends IBusFetcherImpl( resetVector = resetVector, keepPcPlus4 = keepPcPlus4, @@ -183,7 +184,8 @@ class IBusSimplePlugin(resetVector : BigInt, injectorReadyCutGen = false, prediction = prediction, historyRamSizeLog2 = historyRamSizeLog2, - injectorStage = injectorStage){ + injectorStage = injectorStage, + relaxPredictorAddress = relaxPredictorAddress){ var iBus : IBusSimpleBus = null var decodeExceptionPort : Flow[ExceptionCause] = null