From 4209dc27929da0c55f9e8dcdae2ca27269c0745a Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 28 Oct 2020 12:57:20 +0100 Subject: [PATCH 1/5] Fix CsrPlugin privilege crossing --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 668f1b7..0cb6a79 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -1136,7 +1136,11 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep } } - illegalAccess setWhen(privilege < csrAddress(9 downto 8).asUInt) + when(privilege < csrAddress(9 downto 8).asUInt){ + illegalAccess := True + readInstruction := False + writeInstruction := False + } illegalAccess clearWhen(!arbitration.isValid || !input(IS_CSR)) } } From dc9246715de9ef0618f979f2a9ce15e29677b0fd Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 28 Oct 2020 12:58:24 +0100 Subject: [PATCH 2/5] Do not allow jtag ebreak outside machine mode --- src/main/scala/vexriscv/plugin/DebugPlugin.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala index c04d167..516571b 100644 --- a/src/main/scala/vexriscv/plugin/DebugPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala @@ -195,8 +195,9 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount : } } + val allowEBreak = if(!pipeline.serviceExist(classOf[PrivilegeService])) True else pipeline.service(classOf[PrivilegeService]).isMachine() - decode.insert(DO_EBREAK) := !haltIt && (decode.input(IS_EBREAK) || hardwareBreakpoints.map(hb => hb.valid && hb.pc === (decode.input(PC) >> 1)).foldLeft(False)(_ || _)) + decode.insert(DO_EBREAK) := !haltIt && (decode.input(IS_EBREAK) || hardwareBreakpoints.map(hb => hb.valid && hb.pc === (decode.input(PC) >> 1)).foldLeft(False)(_ || _)) && allowEBreak when(execute.arbitration.isValid && execute.input(DO_EBREAK)){ execute.arbitration.haltByOther := True busReadDataReg := execute.input(PC).asBits From d1691e94789950d583e2bb75ee7f26da16a128fa Mon Sep 17 00:00:00 2001 From: banahogg Date: Sat, 14 Nov 2020 17:31:50 -0800 Subject: [PATCH 3/5] Update GCC prebuild instructions for sifive.com reorg --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 57372fc..5d9c15e 100644 --- a/README.md +++ b/README.md @@ -412,7 +412,7 @@ Note that VexRiscv can run Linux on both cache full and cache less design. A prebuild GCC toolsuite can be found here: -- https://www.sifive.com/products/tools/ => SiFive GNU Embedded Toolchain +- https://www.sifive.com/software/ => Prebuilt RISC‑V GCC Toolchain and Emulator The VexRiscvSocSoftware makefiles are expecting to find this prebuild version in /opt/riscv/__contentOfThisPreBuild__ From e0ae46e79491383e1c7caa3e438b4b504d229f86 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 16 Nov 2020 12:37:48 +0100 Subject: [PATCH 4/5] Fix Csr ReadWrite interration with DBusCachedPlugin execute halt # Conflicts: # src/main/scala/vexriscv/plugin/CsrPlugin.scala --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 0cb6a79..545c5fe 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -1010,18 +1010,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep val readData = Bits(32 bits) val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE) val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE) - val writeEnable = writeInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers// && readDataRegValid - val readEnable = readInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers// && !readDataRegValid - //arbitration.isStuckByOthers, in case of the hazardPlugin is in the executeStage - - -// def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT -// val readDataRegValid = Reg(Bool) setWhen(arbitration.isValid) clearWhen(!arbitration.isStuck) -// val writeDataEnable = input(INSTRUCTION)(13) ? writeSrc | B"xFFFFFFFF" -// val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux( -// False -> writeSrc, -// True -> Mux(input(INSTRUCTION)(12), ~writeSrc, writeSrc) -// ) + val writeEnable = writeInstruction && !arbitration.isStuck + val readEnable = readInstruction && !arbitration.isStuck val readToWriteData = CombInit(readData) val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux( From 1b65a9e523341980de46b5b3f92b41bc7b6a1903 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 30 Nov 2020 16:11:00 +0100 Subject: [PATCH 5/5] remove libts-dev from readme --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 5d9c15e..32b2f8a 100644 --- a/README.md +++ b/README.md @@ -296,7 +296,7 @@ sbt "runMain vexriscv.demo.Briey" To run the verilator simulation of the Briey SoC, which can then be connected to OpenOCD/GDB, first get these dependencies: ```sh -sudo apt-get install build-essential xorg-dev libudev-dev libts-dev libgl1-mesa-dev libglu1-mesa-dev libasound2-dev libpulse-dev libopenal-dev libogg-dev libvorbis-dev libaudiofile-dev libpng12-dev libfreetype6-dev libusb-dev libdbus-1-dev zlib1g-dev libdirectfb-dev libsdl2-dev +sudo apt-get install build-essential xorg-dev libudev-dev libgl1-mesa-dev libglu1-mesa-dev libasound2-dev libpulse-dev libopenal-dev libogg-dev libvorbis-dev libaudiofile-dev libpng12-dev libfreetype6-dev libusb-dev libdbus-1-dev zlib1g-dev libdirectfb-dev libsdl2-dev ``` Then go in `src/test/cpp/briey` and run the simulation with (UART TX is printed in the terminal, VGA is displayed in a GUI):