From 14efe6ffda7830d7e222159487b5966aba37336e Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Sun, 21 Apr 2019 20:01:39 +0200 Subject: [PATCH] Riscv software model now implement interrupt priority accordingly to https://github.com/riscv/riscv-isa-sim/commit/496c59d064961bb81e63e2bba1bdadd4abf05a52#diff-a38d447c5232bd448697af4c6c8adb1a changes --- src/test/cpp/regression/main.cpp | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index c77854c..fdb3a4c 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -637,15 +637,19 @@ public: masked = getIp().raw & mideleg & -sEnabled & ie.raw & 0x333; if (masked) { - if (masked & (MIP_MEIP | MIP_SEIP)) - masked &= (MIP_MEIP | MIP_SEIP); - // software interrupts have next-highest priority - else if (masked & (MIP_MSIP | MIP_SSIP)) - masked &= (MIP_MSIP | MIP_SSIP); - // timer interrupts have next-highest priority - else if (masked & (MIP_MTIP | MIP_STIP)) - masked &= (MIP_MTIP | MIP_STIP); - else + if (masked & MIP_MEIP) + masked &= MIP_MEIP; + else if (masked & MIP_MSIP) + masked &= MIP_MSIP; + else if (masked & MIP_MTIP) + masked &= MIP_MTIP; + else if (masked & MIP_SEIP) + masked &= MIP_SEIP; + else if (masked & MIP_SSIP) + masked &= MIP_SSIP; + else if (masked & MIP_STIP) + masked &= MIP_STIP; + else fail(); }