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Riscv software model now implement interrupt priority accordingly to 496c59d064 (diff-a38d447c5232bd448697af4c6c8adb1a) changes

This commit is contained in:
Charles Papon 2019-04-21 20:01:39 +02:00
parent d7ca153c8b
commit 14efe6ffda
1 changed files with 13 additions and 9 deletions
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22
src/test/cpp/regression/main.cpp
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@ -637,15 +637,19 @@ public:
masked = getIp().raw & mideleg & -sEnabled & ie.raw & 0x333; masked = getIp().raw & mideleg & -sEnabled & ie.raw & 0x333;
if (masked) { if (masked) {
if (masked & (MIP_MEIP | MIP_SEIP)) if (masked & MIP_MEIP)
masked &= (MIP_MEIP | MIP_SEIP); masked &= MIP_MEIP;
// software interrupts have next-highest priority else if (masked & MIP_MSIP)
else if (masked & (MIP_MSIP | MIP_SSIP)) masked &= MIP_MSIP;
masked &= (MIP_MSIP | MIP_SSIP); else if (masked & MIP_MTIP)
// timer interrupts have next-highest priority masked &= MIP_MTIP;
else if (masked & (MIP_MTIP | MIP_STIP)) else if (masked & MIP_SEIP)
masked &= (MIP_MTIP | MIP_STIP); masked &= MIP_SEIP;
else else if (masked & MIP_SSIP)
masked &= MIP_SSIP;
else if (masked & MIP_STIP)
masked &= MIP_STIP;
else
fail(); fail();
} }