diff --git a/src/main/scala/vexriscv/plugin/CfuPlugin.scala b/src/main/scala/vexriscv/plugin/CfuPlugin.scala
index d343640..219f962 100644
--- a/src/main/scala/vexriscv/plugin/CfuPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/CfuPlugin.scala
@@ -182,12 +182,13 @@ class CfuPlugin(val stageCount : Int,
       }
     }
 
-    if(withEnable) when(decode.input(CFU_ENABLE) && !csr.en){
+    if(withEnable) when(decode.insert(CFU_ENABLE) && !csr.en){
       pipeline.service(classOf[DecoderService]).forceIllegal()
     }
 
     forkStage plug new Area{
       import forkStage._
+      input(CFU_ENABLE).clearWhen(!input(LEGAL_INSTRUCTION))
       val hazard = stages.dropWhile(_ != forkStage).tail.map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR
       val scheduleWish = arbitration.isValid && input(CFU_ENABLE)
       val schedule = scheduleWish && !hazard
diff --git a/src/main/scala/vexriscv/plugin/FpuPlugin.scala b/src/main/scala/vexriscv/plugin/FpuPlugin.scala
index 8df6fa8..ec9087d 100644
--- a/src/main/scala/vexriscv/plugin/FpuPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/FpuPlugin.scala
@@ -243,7 +243,7 @@ class FpuPlugin(externalFpu : Boolean = false,
     decode plug new Area{
       import decode._
 
-      val trap = decode.input(FPU_ENABLE) && csr.fs === 0 && !stagesFromExecute.map(_.arbitration.isValid).orR
+      val trap = insert(FPU_ENABLE) && csr.fs === 0 && !stagesFromExecute.map(_.arbitration.isValid).orR
       when(trap){
         pipeline.service(classOf[DecoderService]).forceIllegal()
       }
@@ -253,6 +253,7 @@ class FpuPlugin(externalFpu : Boolean = false,
 
       val hazard = csr.pendings.msb || csr.csrActive || csr.fs === 0
 
+      input(FPU_ENABLE).clearWhen(!input(LEGAL_INSTRUCTION))
       arbitration.haltItself setWhen(arbitration.isValid && input(FPU_ENABLE) && hazard)
       arbitration.haltItself setWhen(port.cmd.isStall)