From 15a665af53d351e627ffd3c06630860b6e65a1f7 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Sun, 19 Feb 2023 09:51:18 +0100
Subject: [PATCH] fix too early

---
 .../GenFullWithRiscvPrivilegedDebugJtag.scala | 102 ------------------
 .../scala/vexriscv/demo/SynthesisBench.scala  |  19 +---
 2 files changed, 2 insertions(+), 119 deletions(-)
 delete mode 100644 src/main/scala/vexriscv/demo/GenFullWithRiscvPrivilegedDebugJtag.scala

diff --git a/src/main/scala/vexriscv/demo/GenFullWithRiscvPrivilegedDebugJtag.scala b/src/main/scala/vexriscv/demo/GenFullWithRiscvPrivilegedDebugJtag.scala
deleted file mode 100644
index 7dd17dd..0000000
--- a/src/main/scala/vexriscv/demo/GenFullWithRiscvPrivilegedDebugJtag.scala
+++ /dev/null
@@ -1,102 +0,0 @@
-package vexriscv.demo
-
-import spinal.core._
-import spinal.lib.cpu.riscv.debug.DebugTransportModuleParameter
-import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
-import vexriscv.plugin._
-import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
-
-/**
- * Created by spinalvm on 15.06.17.
- */
-object GenFullWithRiscvPrivilegedDebugJtag extends App{
-  def config = VexRiscvConfig(
-    plugins = List(
-      new IBusCachedPlugin(
-        prediction = DYNAMIC,
-        config = InstructionCacheConfig(
-          cacheSize = 4096,
-          bytePerLine =32,
-          wayCount = 1,
-          addressWidth = 32,
-          cpuDataWidth = 32,
-          memDataWidth = 32,
-          catchIllegalAccess = true,
-          catchAccessFault = true,
-          asyncTagMemory = false,
-          twoCycleRam = true,
-          twoCycleCache = true
-        ),
-        memoryTranslatorPortConfig = MmuPortConfig(
-          portTlbSize = 4
-        )
-      ),
-      new DBusCachedPlugin(
-        config = new DataCacheConfig(
-          cacheSize         = 4096,
-          bytePerLine       = 32,
-          wayCount          = 1,
-          addressWidth      = 32,
-          cpuDataWidth      = 32,
-          memDataWidth      = 32,
-          catchAccessError  = true,
-          catchIllegal      = true,
-          catchUnaligned    = true
-        ),
-        memoryTranslatorPortConfig = MmuPortConfig(
-          portTlbSize = 6
-        )
-      ),
-      new MmuPlugin(
-        virtualRange = _(31 downto 28) === 0xC,
-        ioRange      = _(31 downto 28) === 0xF
-      ),
-      new DecoderSimplePlugin(
-        catchIllegalInstruction = true
-      ),
-      new RegFilePlugin(
-        regFileReadyKind = plugin.SYNC,
-        zeroBoot = false
-      ),
-      new IntAluPlugin,
-      new SrcPlugin(
-        separatedAddSub = false,
-        executeInsertion = true
-      ),
-      new FullBarrelShifterPlugin,
-      new HazardSimplePlugin(
-        bypassExecute           = true,
-        bypassMemory            = true,
-        bypassWriteBack         = true,
-        bypassWriteBackBuffer   = true,
-        pessimisticUseSrc       = false,
-        pessimisticWriteRegFile = false,
-        pessimisticAddressMatch = false
-      ),
-      new MulPlugin,
-      new DivPlugin,
-      new CsrPlugin(CsrPluginConfig.small(0x80000020l).copy(withPrivilegedDebug = true)), //withPrivilegedDebug is required
-      new EmbeddedRiscvJtag(
-        DebugTransportModuleParameter(
-          addressWidth = 7,
-          version      = 1,
-          idle         = 7
-        ),
-        debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")),
-        withTap = true,
-        withTunneling = false
-      ),
-      new BranchPlugin(
-        earlyBranch = false,
-        catchAddressMisaligned = true
-      ),
-      new YamlPlugin("cpu0.yaml")
-    )
-  )
-
-  def cpu() = new VexRiscv(
-    config
-  )
-
-  SpinalVerilog(cpu())
-}
diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala
index d018819..d13645a 100644
--- a/src/main/scala/vexriscv/demo/SynthesisBench.scala
+++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala
@@ -473,22 +473,7 @@ object VexRiscvCustomSynthesisBench {
       cpu
     }
 
-
-    val riscvDebug = new Rtl {
-      override def getName(): String = "riscvDebug"
-      override def getRtlPath(): String = "riscvDebug.v"
-      SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l).copy(withPrivilegedDebug = true)), new EmbeddedRiscvJtag(
-        p = DebugTransportModuleParameter(
-          addressWidth = 7,
-          version      = 1,
-          idle         = 7
-        ),
-        debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")),
-        withTunneling = false,
-        withTap = true
-      )).setDefinitionName(getRtlPath().split("\\.").head))
-    }
-
+    
     val vexDebug = new Rtl {
       override def getName(): String = "vexDebug"
       override def getRtlPath(): String = "vexDebug.v"
@@ -499,7 +484,7 @@ object VexRiscvCustomSynthesisBench {
 
 
     //    val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll, smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced, linuxBalancedSmp)
-    val rtls = List(riscvDebug, vexDebug)
+    val rtls = List(vexDebug)
     //    val rtls = List(smallest)
     val targets = XilinxStdTargets() ++ AlteraStdTargets() ++  IcestormStdTargets().take(1)