diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
index 7fb693d..b58cb0f 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
@@ -126,8 +126,13 @@ object VexRiscvSmpClusterGen {
                      resetVector : Long = 0x80000000l,
                      iBusWidth : Int = 128,
                      dBusWidth : Int = 64,
-                     coherency : Boolean = true) = {
-
+                     coherency : Boolean = true,
+                     iCacheSize : Int = 8192,
+                     dCacheSize : Int = 8192,
+                     iCacheWays : Int = 2,
+                     dCacheWays : Int = 2) = {
+    assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
+    assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
     val config = VexRiscvConfig(
       plugins = List(
         new MmuPlugin(
@@ -143,9 +148,9 @@ object VexRiscvSmpClusterGen {
           injectorStage = false,
           relaxedPcCalculation = false,
           config = InstructionCacheConfig(
-            cacheSize = 4096*2,
+            cacheSize = iCacheSize,
             bytePerLine = 64,
-            wayCount = 2,
+            wayCount = iCacheWays,
             addressWidth = 32,
             cpuDataWidth = 32,
             memDataWidth = iBusWidth,
@@ -169,9 +174,9 @@ object VexRiscvSmpClusterGen {
           dBusRspSlavePipe = true,
           relaxedMemoryTranslationRegister = true,
           config = new DataCacheConfig(
-            cacheSize         = 4096*2,
+            cacheSize         = dCacheSize,
             bytePerLine       = 64,
-            wayCount          = 2,
+            wayCount          = dCacheWays,
             addressWidth      = 32,
             cpuDataWidth      = 32,
             memDataWidth      = dBusWidth,
diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
index 43bcc38..bbf25cd 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
@@ -59,6 +59,10 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
   var cpuCount = 1
   var iBusWidth = 64
   var dBusWidth = 64
+  var iCacheSize = 8192
+  var dCacheSize = 8192
+  var iCacheWays = 2
+  var dCacheWays = 2
   var liteDramWidth = 128
   var coherentDma = false
   var netlistDirectory = "."
@@ -69,6 +73,10 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
     opt[String]("cpu-count") action { (v, c) => cpuCount = v.toInt }
     opt[String]("ibus-width") action { (v, c) => iBusWidth = v.toInt }
     opt[String]("dbus-width") action { (v, c) => dBusWidth = v.toInt }
+    opt[String]("icache-size") action { (v, c) => iCacheSize = v.toInt }
+    opt[String]("dcache-size") action { (v, c) => dCacheSize = v.toInt }
+    opt[String]("icache-ways") action { (v, c) => iCacheWays = v.toInt }
+    opt[String]("dcache-ways") action { (v, c) => dCacheWays = v.toInt }
     opt[String]("litedram-width") action { (v, c) => liteDramWidth = v.toInt }
     opt[String]("netlist-directory") action { (v, c) => netlistDirectory = v }
     opt[String]("netlist-name") action { (v, c) => netlistName = v }
@@ -84,6 +92,10 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
           resetVector = 0,
           iBusWidth = iBusWidth,
           dBusWidth = dBusWidth,
+          iCacheSize = iCacheSize,
+          dCacheSize = dCacheSize,
+          iCacheWays = iCacheWays,
+          dCacheWays = dCacheWays,
           coherency = coherency
         )
       },