diff --git a/README.md b/README.md
index 5c069a8..5aa8daa 100644
--- a/README.md
+++ b/README.md
@@ -438,20 +438,24 @@ class SimdAddPlugin extends Plugin[VexRiscv]{
     import pipeline._
     import pipeline.config._
 
-    //Define some signals used internally to the plugin
-    val rs1 = execute.input(RS1).asUInt //32 bits UInt value of the regfile[RS1]
-    val rs2 = execute.input(RS2).asUInt
-    val rd = UInt(32 bits)
+    //Add a new scope on the execute stage (used to give a name to signals)
+    execute plug new Area {
+      //Define some signals used internally to the plugin
+      val rs1 = execute.input(RS1).asUInt
+      //32 bits UInt value of the regfile[RS1]
+      val rs2 = execute.input(RS2).asUInt
+      val rd = UInt(32 bits)
 
-    //Do some computation
-    rd( 7 downto  0) := rs1( 7 downto  0) + rs2( 7 downto  0)
-    rd(16 downto  8) := rs1(16 downto  8) + rs2(16 downto  8)
-    rd(23 downto 16) := rs1(23 downto 16) + rs2(23 downto 16)
-    rd(31 downto 24) := rs1(31 downto 24) + rs2(31 downto 24)
+      //Do some computation
+      rd(7 downto 0) := rs1(7 downto 0) + rs2(7 downto 0)
+      rd(16 downto 8) := rs1(16 downto 8) + rs2(16 downto 8)
+      rd(23 downto 16) := rs1(23 downto 16) + rs2(23 downto 16)
+      rd(31 downto 24) := rs1(31 downto 24) + rs2(31 downto 24)
 
-    //When the instruction is a SIMD_ADD one, then write the result into the register file data path.
-    when(execute.input(IS_SIMD_ADD)){
-      execute.output(REGFILE_WRITE_DATA) := rd.asBits
+      //When the instruction is a SIMD_ADD one, then write the result into the register file data path.
+      when(execute.input(IS_SIMD_ADD)) {
+        execute.output(REGFILE_WRITE_DATA) := rd.asBits
+      }
     }
   }
 }
@@ -468,4 +472,17 @@ This example is a very simple one, but each plugin can really have access to the
 - Read signals published by other plugins
 - override published signals values
 - Provide an alternative implementation
-- ...
\ No newline at end of file
+- ...
+
+As a demonstrator, this SimdAddPlugin was integrated in the src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala CPU configuration and is self tested by the src/test/cpp/custom/simd_add application by running the following commands :
+
+```sh
+cd src/test/cpp/regression/
+
+# Optionally add TRACE=yes if you want to get the VCD waveform from the simulation.
+# Also you have to know that by default, the testbench introduce instruction/data bus stall.
+# Note the CUSTOM_SIMD_ADD flag is set to yes.
+make clean run IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no DHRYSTONE=no REDO=2 CUSTOM_SIMD_ADD=yes
+```
+
+To retrieve the plugin related signals in the wave, just filter with `simd`.
diff --git a/src/main/scala/vexriscv/demo/CustomInstruction.scala b/src/main/scala/vexriscv/demo/CustomInstruction.scala
index c1bc448..dc35997 100644
--- a/src/main/scala/vexriscv/demo/CustomInstruction.scala
+++ b/src/main/scala/vexriscv/demo/CustomInstruction.scala
@@ -53,20 +53,23 @@ class SimdAddPlugin extends Plugin[VexRiscv]{
     import pipeline._
     import pipeline.config._
 
-    //Define some signals used internally to the plugin
-    val rs1 = execute.input(RS1).asUInt //32 bits UInt value of the regfile[RS1]
-    val rs2 = execute.input(RS2).asUInt
-    val rd = UInt(32 bits)
-    
-    //Do some computation
-    rd( 7 downto  0) := rs1( 7 downto  0) + rs2( 7 downto  0)
-    rd(16 downto  8) := rs1(16 downto  8) + rs2(16 downto  8)
-    rd(23 downto 16) := rs1(23 downto 16) + rs2(23 downto 16)
-    rd(31 downto 24) := rs1(31 downto 24) + rs2(31 downto 24)
+    //Add a new scope on the execute stage (used to give a name to signals)
+    execute plug new Area {
+      //Define some signals used internally to the plugin
+      val rs1 = execute.input(RS1).asUInt //32 bits UInt value of the regfile[RS1]
+      val rs2 = execute.input(RS2).asUInt
+      val rd = UInt(32 bits)
 
-    //When the instruction is a SIMD_ADD one, then write the result into the register file data path.
-    when(execute.input(IS_SIMD_ADD)){
-      execute.output(REGFILE_WRITE_DATA) := rd.asBits
+      //Do some computation
+      rd(7 downto 0) := rs1(7 downto 0) + rs2(7 downto 0)
+      rd(16 downto 8) := rs1(16 downto 8) + rs2(16 downto 8)
+      rd(23 downto 16) := rs1(23 downto 16) + rs2(23 downto 16)
+      rd(31 downto 24) := rs1(31 downto 24) + rs2(31 downto 24)
+
+      //When the instruction is a SIMD_ADD one, then write the result into the register file data path.
+      when(execute.input(IS_SIMD_ADD)) {
+        execute.output(REGFILE_WRITE_DATA) := rd.asBits
+      }
     }
   }
 }
diff --git a/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala b/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala
index 3a082ff..da5b293 100644
--- a/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala
+++ b/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala
@@ -36,12 +36,12 @@ object GenCustomSimdAdd extends App{
           separatedAddSub = false,
           executeInsertion = false
         ),
-        new LightShifterPlugin,
+        new FullBarrielShifterPlugin,
         new HazardSimplePlugin(
-          bypassExecute           = false,
-          bypassMemory            = false,
-          bypassWriteBack         = false,
-          bypassWriteBackBuffer   = false,
+          bypassExecute           = true,
+          bypassMemory            = true,
+          bypassWriteBack         = true,
+          bypassWriteBackBuffer   = true,
           pessimisticUseSrc       = false,
           pessimisticWriteRegFile = false,
           pessimisticAddressMatch = false