From 1752b5f184b38347bff4824a0e1235a70c6cae6c Mon Sep 17 00:00:00 2001
From: Dolu1990 <papuchoud@hotmail.com>
Date: Sun, 27 May 2018 23:39:49 +0200
Subject: [PATCH] Give name to inter stages registers

---
 src/main/scala/vexriscv/Pipeline.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/vexriscv/Pipeline.scala b/src/main/scala/vexriscv/Pipeline.scala
index 86a2018..19fbbbf 100644
--- a/src/main/scala/vexriscv/Pipeline.scala
+++ b/src/main/scala/vexriscv/Pipeline.scala
@@ -100,7 +100,7 @@ trait Pipeline {
             inputDefault := stage.inserts(key)
           } else {
             val stageBefore = stages(stageIndex - 1)
-            inputDefault := RegNextWhen(stageBefore.output(key), !stage.arbitration.isStuck)
+            inputDefault := RegNextWhen(stageBefore.output(key), !stage.arbitration.isStuck).setName(s"${stageBefore.getName()}_to_${stage.getName()}_${key.getName()}")
           }
         }
       }