From 179e7f7b4caeee5805227a41b0da8c4169fe7b1d Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Wed, 5 Apr 2017 14:25:11 +0200
Subject: [PATCH] IBusCachedPlugin add asyncTagMemory option

---
 .../SpinalRiscv/Plugin/IBusCachedPlugin.scala | 54 ++++++++++---------
 src/test/cpp/testA/main.cpp                   |  2 +
 2 files changed, 32 insertions(+), 24 deletions(-)

diff --git a/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala b/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala
index 603ce74..f80cdfa 100644
--- a/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala
+++ b/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala
@@ -12,7 +12,8 @@ case class InstructionCacheConfig( cacheSize : Int,
                                    addressWidth : Int,
                                    cpuDataWidth : Int,
                                    memDataWidth : Int,
-                                   catchAccessFault : Boolean){
+                                   catchAccessFault : Boolean,
+                                   asyncTagMemory : Boolean){
   def burstSize = bytePerLine*8/memDataWidth
 }
 
@@ -282,7 +283,12 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
 
     val waysRead = for(way <- ways) yield new Area{
       val readAddress = Mux(io.cpu.fetch.isStuck,io.cpu.fetch.address,io.cpu.prefetch.address)
-      val tag = way.tags.readSync(readAddress(lineRange))
+//      val readAddress = io.cpu.prefetch.address
+      val tag = if(asyncTagMemory)
+        way.tags.readAsync(io.cpu.fetch.address(lineRange))
+      else
+        way.tags.readSync(readAddress(lineRange))
+
       val data = way.datas.readSync(readAddress(lineRange.high downto wordRange.low))
       //      val readAddress = request.address
       //      val tag = way.tags.readAsync(readAddress(lineRange))
@@ -314,25 +320,25 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
 
   io.flush.cmd.ready := !(lineLoader.request.valid || io.cpu.fetch.isValid)
 }
-
-object InstructionCacheMain{
-
-  def main(args: Array[String]) {
-    implicit val p = InstructionCacheConfig(
-      cacheSize =4096,
-      bytePerLine =32,
-      wayCount = 1,
-      wrappedMemAccess = true,
-      addressWidth = 32,
-      cpuDataWidth = 32,
-      memDataWidth = 32,
-      catchAccessFault = true)
-    //    val io = new Bundle{
-    //      val cpu = slave(InstructionCacheCpuBus())
-    //      val mem = master(InstructionCacheMemBus())
-    //    }
-
-    SpinalVhdl(new InstructionCache(p))
-  }
-}
-
+//
+//object InstructionCacheMain{
+//
+//  def main(args: Array[String]) {
+//    implicit val p = InstructionCacheConfig(
+//      cacheSize =4096,
+//      bytePerLine =32,
+//      wayCount = 1,
+//      wrappedMemAccess = true,
+//      addressWidth = 32,
+//      cpuDataWidth = 32,
+//      memDataWidth = 32,
+//      catchAccessFault = true)
+//    //    val io = new Bundle{
+//    //      val cpu = slave(InstructionCacheCpuBus())
+//    //      val mem = master(InstructionCacheMemBus())
+//    //    }
+//
+//    SpinalVhdl(new InstructionCache(p))
+//  }
+//}
+//
diff --git a/src/test/cpp/testA/main.cpp b/src/test/cpp/testA/main.cpp
index 0b50faf..cc8fcc6 100644
--- a/src/test/cpp/testA/main.cpp
+++ b/src/test/cpp/testA/main.cpp
@@ -457,7 +457,9 @@ public:
 		top->iBus_rsp_valid = 0;
 		if(pendingCount != 0 && (!ws->iStall || VL_RANDOM_I(7) < 100)){
 			ws->iBusAccess(address,&top->iBus_rsp_payload_data,&error);
+			#ifdef CSR
 			top->iBus_rsp_payload_error = error;
+			#endif
 			pendingCount--;
 			address = (address & ~0x1F) + ((address + 4) & 0x1F);
 			top->iBus_rsp_valid = 1;