diff --git a/src/main/c/emulator/build/emulator.asm b/src/main/c/emulator/build/emulator.asm index 5893188..dffc897 100644 --- a/src/main/c/emulator/build/emulator.asm +++ b/src/main/c/emulator/build/emulator.asm @@ -12,19 +12,19 @@ Disassembly of section .init: #endif*/ la sp, _sp 80000000: 00001117 auipc sp,0x1 -80000004: cb010113 addi sp,sp,-848 # 80000cb0 <_sp> +80000004: dd810113 addi sp,sp,-552 # 80000dd8 <_sp> /* Load data section */ la a0, _data_lma 80000008: 00000517 auipc a0,0x0 -8000000c: 43450513 addi a0,a0,1076 # 8000043c <__init_array_end> +8000000c: 55c50513 addi a0,a0,1372 # 80000564 <__init_array_end> la a1, _data 80000010: 00000597 auipc a1,0x0 -80000014: 42c58593 addi a1,a1,1068 # 8000043c <__init_array_end> +80000014: 55458593 addi a1,a1,1364 # 80000564 <__init_array_end> la a2, _edata 80000018: 00000617 auipc a2,0x0 -8000001c: 49860613 addi a2,a2,1176 # 800004b0 <__bss_start> +8000001c: 5c060613 addi a2,a2,1472 # 800005d8 <__bss_start> bgeu a1, a2, 2f 80000020: 00c5fc63 bleu a2,a1,80000038 <_start+0x38> 1: @@ -43,10 +43,10 @@ Disassembly of section .init: /* Clear bss section */ la a0, __bss_start 80000038: 00000517 auipc a0,0x0 -8000003c: 47850513 addi a0,a0,1144 # 800004b0 <__bss_start> +8000003c: 5a050513 addi a0,a0,1440 # 800005d8 <__bss_start> la a1, _end 80000040: 00000597 auipc a1,0x0 -80000044: 47058593 addi a1,a1,1136 # 800004b0 <__bss_start> +80000044: 59858593 addi a1,a1,1432 # 800005d8 <__bss_start> bgeu a0, a1, 2f 80000048: 00b57863 bleu a1,a0,80000058 <_start+0x58> 1: @@ -59,7 +59,7 @@ Disassembly of section .init: 2: call __libc_init_array -80000058: 34c000ef jal ra,800003a4 <__libc_init_array> +80000058: 474000ef jal ra,800004cc <__libc_init_array> call init 8000005c: 128000ef jal ra,80000184 la ra, done @@ -156,7 +156,7 @@ trapEntry: sw x31, 31*4(sp) 800000f8: 07f12e23 sw t6,124(sp) call trap -800000fc: 134000ef jal ra,80000230 +800000fc: 1e8000ef jal ra,800002e4 lw x0, 0*4(sp) 80000100: 00012003 lw zero,0(sp) lw x1, 1*4(sp) @@ -227,20 +227,18 @@ trapEntry: Disassembly of section .text: 80000184 : - -extern const unsigned int _sp; extern void trapEntry(); +extern void emulationTrap(); void init() { + unsigned int sp = (unsigned int) (&_sp); csr_write(mtvec, trapEntry); 80000184: 800007b7 lui a5,0x80000 -80000188: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xfffff3cc> +80000188: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xfffff2a4> 8000018c: 30579073 csrw mtvec,a5 - - unsigned int sp = (unsigned int) (&_sp); -80000190: 800017b7 lui a5,0x80001 -80000194: cb078793 addi a5,a5,-848 # 80000cb0 <_sp+0x0> csr_write(mscratch, sp -32*4); +80000190: 800017b7 lui a5,0x80001 +80000194: dd878793 addi a5,a5,-552 # 80000dd8 <_sp+0x0> 80000198: f8078793 addi a5,a5,-128 8000019c: 34079073 csrw mscratch,a5 csr_write(mstatus, 0x0800); @@ -263,10 +261,10 @@ int readRegister(int id){ return ((int*) sp)[id-32]; 800001c0: 00251513 slli a0,a0,0x2 800001c4: 800017b7 lui a5,0x80001 -800001c8: cb078793 addi a5,a5,-848 # 80000cb0 <_sp+0x0> +800001c8: dd878793 addi a5,a5,-552 # 80000dd8 <_sp+0x0> 800001cc: 00f50533 add a0,a0,a5 } -800001d0: f8052503 lw a0,-128(a0) # 80ffff80 <_sp+0xfff2d0> +800001d0: f8052503 lw a0,-128(a0) # 80ffff80 <_sp+0xfff1a8> 800001d4: 00008067 ret 800001d8 : @@ -275,7 +273,7 @@ void writeRegister(int id, int value){ ((int*) sp)[id-32] = value; 800001d8: 00251513 slli a0,a0,0x2 800001dc: 800017b7 lui a5,0x80001 -800001e0: cb078793 addi a5,a5,-848 # 80000cb0 <_sp+0x0> +800001e0: dd878793 addi a5,a5,-552 # 80000dd8 <_sp+0x0> 800001e4: 00f50533 add a0,a0,a5 800001e8: f8b52023 sw a1,-128(a0) } @@ -286,7 +284,7 @@ void writeRegister(int id, int value){ void stopSim(){ *((volatile int*) SIM_STOP) = 0; -800001f0: fe002e23 sw zero,-4(zero) # fffffffc <_sp+0x7ffff34c> +800001f0: fe002e23 sw zero,-4(zero) # fffffffc <_sp+0x7ffff224> } 800001f4: 00008067 ret @@ -294,7 +292,7 @@ void stopSim(){ void putC(char c){ *((volatile int*) PUTC) = c; -800001f8: fea02c23 sw a0,-8(zero) # fffffff8 <_sp+0x7ffff348> +800001f8: fea02c23 sw a0,-8(zero) # fffffff8 <_sp+0x7ffff220> } 800001fc: 00008067 ret @@ -315,195 +313,319 @@ void redirectTrap(){ csr_write(scause, csr_read(mcause)); 8000021c: 342027f3 csrr a5,mcause 80000220: 14279073 csrw scause,a5 + csr_write(mepc, csr_read(stvec)); +80000224: 105027f3 csrr a5,stvec +80000228: 34179073 csrw mepc,a5 } -80000224: 00c12083 lw ra,12(sp) -80000228: 01010113 addi sp,sp,16 -8000022c: 00008067 ret +8000022c: 00c12083 lw ra,12(sp) +80000230: 01010113 addi sp,sp,16 +80000234: 00008067 ret + +80000238 : + +void emulationTrapToSupervisorTrap(uint32_t sepc, uint32_t mstatus){ + csr_write(sbadaddr, csr_read(mbadaddr)); +80000238: 343027f3 csrr a5,mbadaddr +8000023c: 14379073 csrw sbadaddr,a5 + csr_write(scause, csr_read(mcause)); +80000240: 342027f3 csrr a5,mcause +80000244: 14279073 csrw scause,a5 + csr_write(sepc, sepc); +80000248: 14151073 csrw sepc,a0 + csr_write(mepc, csr_read(stvec)); +8000024c: 105027f3 csrr a5,stvec +80000250: 34179073 csrw mepc,a5 + csr_clear(sstatus, MSTATUS_SPP); +80000254: 10000793 li a5,256 +80000258: 1007b073 csrc sstatus,a5 + csr_set(sstatus, (mstatus >> 3) & MSTATUS_SPP); +8000025c: 0035d593 srli a1,a1,0x3 +80000260: 1005f593 andi a1,a1,256 +80000264: 1005a073 csrs sstatus,a1 + csr_clear(mstatus, MSTATUS_MPP); +80000268: 000027b7 lui a5,0x2 +8000026c: 80078793 addi a5,a5,-2048 # 1800 <__stack_size+0x1000> +80000270: 3007b073 csrc mstatus,a5 + csr_set(mstatus, 0x8000); +80000274: 000087b7 lui a5,0x8 +80000278: 3007a073 csrs mstatus,a5 +} +8000027c: 00008067 ret + +80000280 : + +//Will modify MEPC +int readWord(int address, int *data){ + int result, tmp; + int failed; + __asm__ __volatile__ ( +80000280: 00020737 lui a4,0x20 +80000284: 30072073 csrs mstatus,a4 +80000288: 00000717 auipc a4,0x0 +8000028c: 01870713 addi a4,a4,24 # 800002a0 +80000290: 34171073 csrw mepc,a4 +80000294: 00100693 li a3,1 +80000298: 00052783 lw a5,0(a0) +8000029c: 00000693 li a3,0 +800002a0: 00020737 lui a4,0x20 +800002a4: 30073073 csrc mstatus,a4 +800002a8: 00068513 mv a0,a3 + : [result]"=&r" (result), [failed]"=&r" (failed), [tmp]"=&r" (tmp) + : [address]"r" (address) + : "memory" + ); + + *data = result; +800002ac: 00f5a023 sw a5,0(a1) + return failed; +} +800002b0: 00008067 ret + +800002b4 : + +//Will modify MEPC +int writeWord(uint32_t address, uint32_t data){ + int result, tmp; + int failed; + __asm__ __volatile__ ( +800002b4: 00020737 lui a4,0x20 +800002b8: 30072073 csrs mstatus,a4 +800002bc: 00000717 auipc a4,0x0 +800002c0: 01870713 addi a4,a4,24 # 800002d4 +800002c4: 34171073 csrw mepc,a4 +800002c8: 00100793 li a5,1 +800002cc: 00b52023 sw a1,0(a0) +800002d0: 00000793 li a5,0 +800002d4: 00020737 lui a4,0x20 +800002d8: 30073073 csrc mstatus,a4 +800002dc: 00078513 mv a0,a5 + : [address]"r" (address), [data]"r" (data) + : "memory" + ); + + return failed; +} +800002e0: 00008067 ret + +800002e4 : + + + -80000230 : -#define min(a,b) \ - ({ __typeof__ (a) _a = (a); \ - __typeof__ (b) _b = (b); \ - _a < _b ? _a : _b; }) void trap(){ -80000230: fe010113 addi sp,sp,-32 -80000234: 00112e23 sw ra,28(sp) -80000238: 00812c23 sw s0,24(sp) -8000023c: 00912a23 sw s1,20(sp) -80000240: 01212823 sw s2,16(sp) -80000244: 01312623 sw s3,12(sp) +800002e4: fd010113 addi sp,sp,-48 +800002e8: 02112623 sw ra,44(sp) +800002ec: 02812423 sw s0,40(sp) +800002f0: 02912223 sw s1,36(sp) +800002f4: 03212023 sw s2,32(sp) +800002f8: 01312e23 sw s3,28(sp) +800002fc: 01412c23 sw s4,24(sp) +80000300: 01512a23 sw s5,20(sp) int cause = csr_read(mcause); -80000248: 342027f3 csrr a5,mcause +80000304: 342027f3 csrr a5,mcause if(cause < 0){ -8000024c: 0207ca63 bltz a5,80000280 +80000308: 0207ce63 bltz a5,80000344 redirectTrap(); } else { switch(cause){ -80000250: 00200713 li a4,2 -80000254: 02e78a63 beq a5,a4,80000288 -80000258: 00900713 li a4,9 -8000025c: 10e78863 beq a5,a4,8000036c +8000030c: 00200713 li a4,2 +80000310: 02e78e63 beq a5,a4,8000034c +80000314: 00900713 li a4,9 +80000318: 16e78e63 beq a5,a4,80000494 csr_write(mepc, csr_read(mepc) + 4); }break; default: stopSim(); break; } }break; default: redirectTrap(); break; -80000260: fa1ff0ef jal ra,80000200 +8000031c: ee5ff0ef jal ra,80000200 } } } -80000264: 01c12083 lw ra,28(sp) -80000268: 01812403 lw s0,24(sp) -8000026c: 01412483 lw s1,20(sp) -80000270: 01012903 lw s2,16(sp) -80000274: 00c12983 lw s3,12(sp) -80000278: 02010113 addi sp,sp,32 -8000027c: 00008067 ret +80000320: 02c12083 lw ra,44(sp) +80000324: 02812403 lw s0,40(sp) +80000328: 02412483 lw s1,36(sp) +8000032c: 02012903 lw s2,32(sp) +80000330: 01c12983 lw s3,28(sp) +80000334: 01812a03 lw s4,24(sp) +80000338: 01412a83 lw s5,20(sp) +8000033c: 03010113 addi sp,sp,48 +80000340: 00008067 ret redirectTrap(); -80000280: f81ff0ef jal ra,80000200 -80000284: fe1ff06f j 80000264 +80000344: ebdff0ef jal ra,80000200 +80000348: fd9ff06f j 80000320 + int mepc = csr_read(mepc); +8000034c: 341024f3 csrr s1,mepc + int mstatus = csr_read(mstatus); +80000350: 300029f3 csrr s3,mstatus int instruction = csr_read(mbadaddr); -80000288: 34302473 csrr s0,mbadaddr +80000354: 34302473 csrr s0,mbadaddr int opcode = instruction & 0x7F; -8000028c: 07f47693 andi a3,s0,127 +80000358: 07f47693 andi a3,s0,127 int funct3 = (instruction >> 12) & 0x7; -80000290: 40c45793 srai a5,s0,0xc -80000294: 0077f793 andi a5,a5,7 +8000035c: 40c45793 srai a5,s0,0xc +80000360: 0077f793 andi a5,a5,7 switch(opcode){ -80000298: 02f00713 li a4,47 -8000029c: fce694e3 bne a3,a4,80000264 +80000364: 02f00713 li a4,47 +80000368: fae69ce3 bne a3,a4,80000320 switch(funct3){ -800002a0: 00200713 li a4,2 -800002a4: 0ce79063 bne a5,a4,80000364 +8000036c: 00200713 li a4,2 +80000370: 10e79e63 bne a5,a4,8000048c int sel = instruction >> 27; -800002a8: 41b45493 srai s1,s0,0x1b - int*addr = (int*)readRegister((instruction >> 15) & 0x1F); -800002ac: 40f45513 srai a0,s0,0xf -800002b0: 01f57513 andi a0,a0,31 -800002b4: f0dff0ef jal ra,800001c0 -800002b8: 00050993 mv s3,a0 - int src = readRegister((instruction >> 20) & 0x1F); -800002bc: 41445513 srai a0,s0,0x14 -800002c0: 01f57513 andi a0,a0,31 -800002c4: efdff0ef jal ra,800001c0 -800002c8: 00050913 mv s2,a0 - int rd = (instruction >> 7) & 0x1F; -800002cc: 40745413 srai s0,s0,0x7 -800002d0: 01f47513 andi a0,s0,31 - int readValue = *addr; -800002d4: 0009a583 lw a1,0(s3) - switch(sel){ -800002d8: 01c00793 li a5,28 -800002dc: 0897e063 bltu a5,s1,8000035c -800002e0: 00249493 slli s1,s1,0x2 -800002e4: 800007b7 lui a5,0x80000 -800002e8: 43c78793 addi a5,a5,1084 # 8000043c <_sp+0xfffff78c> -800002ec: 00f484b3 add s1,s1,a5 -800002f0: 0004a783 lw a5,0(s1) -800002f4: 00078067 jr a5 - case 0x0: writeValue = src + readValue; break; -800002f8: 00b90933 add s2,s2,a1 - writeRegister(rd, readValue); -800002fc: eddff0ef jal ra,800001d8 - *addr = writeValue; -80000300: 0129a023 sw s2,0(s3) - csr_write(mepc, csr_read(mepc) + 4); -80000304: 341027f3 csrr a5,mepc -80000308: 00478793 addi a5,a5,4 -8000030c: 34179073 csrw mepc,a5 - }break; -80000310: f55ff06f j 80000264 - case 0x4: writeValue = src ^ readValue; break; -80000314: 00b94933 xor s2,s2,a1 -80000318: fe5ff06f j 800002fc - case 0xC: writeValue = src & readValue; break; -8000031c: 00b97933 and s2,s2,a1 -80000320: fddff06f j 800002fc - case 0x8: writeValue = src | readValue; break; -80000324: 00b96933 or s2,s2,a1 -80000328: fd5ff06f j 800002fc - case 0x10: writeValue = min(src, readValue); break; -8000032c: fd25d8e3 ble s2,a1,800002fc -80000330: 00058913 mv s2,a1 -80000334: fc9ff06f j 800002fc - case 0x14: writeValue = max(src, readValue); break; -80000338: fcb952e3 ble a1,s2,800002fc -8000033c: 00058913 mv s2,a1 -80000340: fbdff06f j 800002fc - case 0x18: writeValue = min((unsigned int)src, (unsigned int)readValue); break; -80000344: fb25fce3 bleu s2,a1,800002fc -80000348: 00058913 mv s2,a1 -8000034c: fb1ff06f j 800002fc - case 0x1C: writeValue = max((unsigned int)src, (unsigned int)readValue); break; -80000350: fab976e3 bleu a1,s2,800002fc -80000354: 00058913 mv s2,a1 -80000358: fa5ff06f j 800002fc - default: redirectTrap(); return; break; -8000035c: ea5ff0ef jal ra,80000200 -80000360: f05ff06f j 80000264 - default: redirectTrap(); break; -80000364: e9dff0ef jal ra,80000200 -80000368: efdff06f j 80000264 - int which = readRegister(17); -8000036c: 01100513 li a0,17 -80000370: e51ff0ef jal ra,800001c0 - switch(which){ -80000374: 00100793 li a5,1 -80000378: 02f51263 bne a0,a5,8000039c - putC(readRegister(10)); -8000037c: 00a00513 li a0,10 +80000374: 41b45913 srai s2,s0,0x1b + int addr = readRegister((instruction >> 15) & 0x1F); +80000378: 40f45513 srai a0,s0,0xf +8000037c: 01f57513 andi a0,a0,31 80000380: e41ff0ef jal ra,800001c0 -80000384: 0ff57513 andi a0,a0,255 -80000388: e71ff0ef jal ra,800001f8 +80000384: 00050a93 mv s5,a0 + int src = readRegister((instruction >> 20) & 0x1F); +80000388: 41445513 srai a0,s0,0x14 +8000038c: 01f57513 andi a0,a0,31 +80000390: e31ff0ef jal ra,800001c0 +80000394: 00050a13 mv s4,a0 + int rd = (instruction >> 7) & 0x1F; +80000398: 40745413 srai s0,s0,0x7 +8000039c: 01f47413 andi s0,s0,31 + if(readWord(addr, &readValue)){ +800003a0: 00c10593 addi a1,sp,12 +800003a4: 000a8513 mv a0,s5 +800003a8: ed9ff0ef jal ra,80000280 +800003ac: 02051263 bnez a0,800003d0 + switch(sel){ +800003b0: 01c00793 li a5,28 +800003b4: 0d27e063 bltu a5,s2,80000474 +800003b8: 00291913 slli s2,s2,0x2 +800003bc: 800007b7 lui a5,0x80000 +800003c0: 56478793 addi a5,a5,1380 # 80000564 <_sp+0xfffff78c> +800003c4: 00f90933 add s2,s2,a5 +800003c8: 00092783 lw a5,0(s2) +800003cc: 00078067 jr a5 + emulationTrapToSupervisorTrap(mepc, mstatus); +800003d0: 00098593 mv a1,s3 +800003d4: 00048513 mv a0,s1 +800003d8: e61ff0ef jal ra,80000238 + return; +800003dc: f45ff06f j 80000320 + case 0x0: writeValue = src + readValue; break; +800003e0: 00c12783 lw a5,12(sp) +800003e4: 00fa0a33 add s4,s4,a5 + writeRegister(rd, readValue); +800003e8: 00c12583 lw a1,12(sp) +800003ec: 00040513 mv a0,s0 +800003f0: de9ff0ef jal ra,800001d8 + if(writeWord(addr, writeValue)){ +800003f4: 000a0593 mv a1,s4 +800003f8: 000a8513 mv a0,s5 +800003fc: eb9ff0ef jal ra,800002b4 +80000400: 06051e63 bnez a0,8000047c + csr_write(mepc, mepc + 4); +80000404: 00448493 addi s1,s1,4 +80000408: 34149073 csrw mepc,s1 + }break; +8000040c: f15ff06f j 80000320 + case 0x4: writeValue = src ^ readValue; break; +80000410: 00c12783 lw a5,12(sp) +80000414: 00fa4a33 xor s4,s4,a5 +80000418: fd1ff06f j 800003e8 + case 0xC: writeValue = src & readValue; break; +8000041c: 00c12783 lw a5,12(sp) +80000420: 00fa7a33 and s4,s4,a5 +80000424: fc5ff06f j 800003e8 + case 0x8: writeValue = src | readValue; break; +80000428: 00c12783 lw a5,12(sp) +8000042c: 00fa6a33 or s4,s4,a5 +80000430: fb9ff06f j 800003e8 + case 0x10: writeValue = min(src, readValue); break; +80000434: 00c12783 lw a5,12(sp) +80000438: fb47d8e3 ble s4,a5,800003e8 +8000043c: 00078a13 mv s4,a5 +80000440: fa9ff06f j 800003e8 + case 0x14: writeValue = max(src, readValue); break; +80000444: 00c12783 lw a5,12(sp) +80000448: fafa50e3 ble a5,s4,800003e8 +8000044c: 00078a13 mv s4,a5 +80000450: f99ff06f j 800003e8 + case 0x18: writeValue = min((unsigned int)src, (unsigned int)readValue); break; +80000454: 00c12783 lw a5,12(sp) +80000458: f947f8e3 bleu s4,a5,800003e8 +8000045c: 00078a13 mv s4,a5 +80000460: f89ff06f j 800003e8 + case 0x1C: writeValue = max((unsigned int)src, (unsigned int)readValue); break; +80000464: 00c12783 lw a5,12(sp) +80000468: f8fa70e3 bleu a5,s4,800003e8 +8000046c: 00078a13 mv s4,a5 +80000470: f79ff06f j 800003e8 + default: redirectTrap(); return; break; +80000474: d8dff0ef jal ra,80000200 +80000478: ea9ff06f j 80000320 + emulationTrapToSupervisorTrap(mepc, mstatus); +8000047c: 00098593 mv a1,s3 +80000480: 00048513 mv a0,s1 +80000484: db5ff0ef jal ra,80000238 + return; +80000488: e99ff06f j 80000320 + default: redirectTrap(); break; +8000048c: d75ff0ef jal ra,80000200 +80000490: e91ff06f j 80000320 + int which = readRegister(17); +80000494: 01100513 li a0,17 +80000498: d29ff0ef jal ra,800001c0 + switch(which){ +8000049c: 00100793 li a5,1 +800004a0: 02f51263 bne a0,a5,800004c4 + putC(readRegister(10)); +800004a4: 00a00513 li a0,10 +800004a8: d19ff0ef jal ra,800001c0 +800004ac: 0ff57513 andi a0,a0,255 +800004b0: d49ff0ef jal ra,800001f8 csr_write(mepc, csr_read(mepc) + 4); -8000038c: 341027f3 csrr a5,mepc -80000390: 00478793 addi a5,a5,4 -80000394: 34179073 csrw mepc,a5 +800004b4: 341027f3 csrr a5,mepc +800004b8: 00478793 addi a5,a5,4 +800004bc: 34179073 csrw mepc,a5 }break; -80000398: ecdff06f j 80000264 +800004c0: e61ff06f j 80000320 default: stopSim(); break; -8000039c: e55ff0ef jal ra,800001f0 -800003a0: ec5ff06f j 80000264 +800004c4: d2dff0ef jal ra,800001f0 +800004c8: e59ff06f j 80000320 -800003a4 <__libc_init_array>: -800003a4: ff010113 addi sp,sp,-16 -800003a8: 00812423 sw s0,8(sp) -800003ac: 00912223 sw s1,4(sp) -800003b0: 00000417 auipc s0,0x0 -800003b4: 08c40413 addi s0,s0,140 # 8000043c <__init_array_end> -800003b8: 00000497 auipc s1,0x0 -800003bc: 08448493 addi s1,s1,132 # 8000043c <__init_array_end> -800003c0: 408484b3 sub s1,s1,s0 -800003c4: 01212023 sw s2,0(sp) -800003c8: 00112623 sw ra,12(sp) -800003cc: 4024d493 srai s1,s1,0x2 -800003d0: 00000913 li s2,0 -800003d4: 04991063 bne s2,s1,80000414 <__libc_init_array+0x70> -800003d8: 00000417 auipc s0,0x0 -800003dc: 06440413 addi s0,s0,100 # 8000043c <__init_array_end> -800003e0: 00000497 auipc s1,0x0 -800003e4: 05c48493 addi s1,s1,92 # 8000043c <__init_array_end> -800003e8: 408484b3 sub s1,s1,s0 -800003ec: c8dff0ef jal ra,80000078 <_init> -800003f0: 4024d493 srai s1,s1,0x2 -800003f4: 00000913 li s2,0 -800003f8: 02991863 bne s2,s1,80000428 <__libc_init_array+0x84> -800003fc: 00c12083 lw ra,12(sp) -80000400: 00812403 lw s0,8(sp) -80000404: 00412483 lw s1,4(sp) -80000408: 00012903 lw s2,0(sp) -8000040c: 01010113 addi sp,sp,16 -80000410: 00008067 ret -80000414: 00042783 lw a5,0(s0) -80000418: 00190913 addi s2,s2,1 -8000041c: 00440413 addi s0,s0,4 -80000420: 000780e7 jalr a5 -80000424: fb1ff06f j 800003d4 <__libc_init_array+0x30> -80000428: 00042783 lw a5,0(s0) -8000042c: 00190913 addi s2,s2,1 -80000430: 00440413 addi s0,s0,4 -80000434: 000780e7 jalr a5 -80000438: fc1ff06f j 800003f8 <__libc_init_array+0x54> +800004cc <__libc_init_array>: +800004cc: ff010113 addi sp,sp,-16 +800004d0: 00812423 sw s0,8(sp) +800004d4: 00912223 sw s1,4(sp) +800004d8: 00000417 auipc s0,0x0 +800004dc: 08c40413 addi s0,s0,140 # 80000564 <__init_array_end> +800004e0: 00000497 auipc s1,0x0 +800004e4: 08448493 addi s1,s1,132 # 80000564 <__init_array_end> +800004e8: 408484b3 sub s1,s1,s0 +800004ec: 01212023 sw s2,0(sp) +800004f0: 00112623 sw ra,12(sp) +800004f4: 4024d493 srai s1,s1,0x2 +800004f8: 00000913 li s2,0 +800004fc: 04991063 bne s2,s1,8000053c <__libc_init_array+0x70> +80000500: 00000417 auipc s0,0x0 +80000504: 06440413 addi s0,s0,100 # 80000564 <__init_array_end> +80000508: 00000497 auipc s1,0x0 +8000050c: 05c48493 addi s1,s1,92 # 80000564 <__init_array_end> +80000510: 408484b3 sub s1,s1,s0 +80000514: b65ff0ef jal ra,80000078 <_init> +80000518: 4024d493 srai s1,s1,0x2 +8000051c: 00000913 li s2,0 +80000520: 02991863 bne s2,s1,80000550 <__libc_init_array+0x84> +80000524: 00c12083 lw ra,12(sp) +80000528: 00812403 lw s0,8(sp) +8000052c: 00412483 lw s1,4(sp) +80000530: 00012903 lw s2,0(sp) +80000534: 01010113 addi sp,sp,16 +80000538: 00008067 ret +8000053c: 00042783 lw a5,0(s0) +80000540: 00190913 addi s2,s2,1 +80000544: 00440413 addi s0,s0,4 +80000548: 000780e7 jalr a5 +8000054c: fb1ff06f j 800004fc <__libc_init_array+0x30> +80000550: 00042783 lw a5,0(s0) +80000554: 00190913 addi s2,s2,1 +80000558: 00440413 addi s0,s0,4 +8000055c: 000780e7 jalr a5 +80000560: fc1ff06f j 80000520 <__libc_init_array+0x54> diff --git a/src/main/c/emulator/build/emulator.hex b/src/main/c/emulator/build/emulator.hex index f70c1b4..7aba567 100644 --- a/src/main/c/emulator/build/emulator.hex +++ b/src/main/c/emulator/build/emulator.hex @@ -1,10 +1,10 @@ :0200000480007A -:1000000017110000130101CB17050000130545432C -:10001000970500009385C542170600001306864920 +:1000000017110000130181DD170500001305C55508 +:100010009705000093854555170600001306065CFA :1000200063FCC5008322050023A05500130545008D -:1000300093854500E3E8C5FE1705000013058547D5 -:1000400097050000938505476378B50023200500D8 -:1000500013054500E36CB5FEEF00C034EF008012DD +:1000300093854500E3E8C5FE170500001305055A42 +:1000400097050000938585596378B5002320050046 +:1000500013054500E36CB5FEEF004047EF0080124A :100060009700000093804001370500819305000050 :10007000730020306F0000006780000073110134AE :1000800023200100232211002326310023284100D0 @@ -14,7 +14,7 @@ :1000C0002322110523242105232631052328410558 :1000D000232A5105232C6105232E71052320810736 :1000E000232291072324A1072326B1072328C10730 -:1000F000232AD107232CE107232EF107EF00401319 +:1000F000232AD107232CE107232EF107EF00801ECE :1001000003200100832041008321C100032201015B :1001100083224101032381018323C10103240102BE :1001200083244102032581028325C10203260103A2 @@ -25,56 +25,74 @@ :10017000832E4107032F8107832FC1077311013499 :0401800073002030B8 :10018400B70700809387C70773905730B71700806D -:10019400938707CB938707F873900734B71700004A +:10019400938787DD938707F873900734B7170000B8 :1001A4009387078073900730B70700C073901734A4 :1001B400B7B700007390273067800000131525003F -:1001C400B7170080938707CB3305F500032505F89F -:1001D4006780000013152500B7170080938707CBAD +:1001C400B7170080938787DD3305F500032505F80D +:1001D4006780000013152500B7170080938787DD1B :1001E4003305F5002320B5F867800000232E00FEB8 :1001F40067800000232CA0FE67800000130101FF2C :1002040023261100EFF09FFEF32730347390371448 :10021400F327103473901714F327203473902714A2 -:100224008320C1001301010167800000130101FE56 -:10023400232E1100232C8100232A9100232821013D -:1002440023263101F327203463CA07021307200051 -:10025400638AE702130790006388E710EFF01FFA40 -:100264008320C10103248101832441010329010165 -:100274008329C1001301010267800000EFF01FF819 -:100284006FF01FFE732430349376F4079357C44001 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+:1005840028040080740400807404008074040080D3 +:100594001C040080740400807404008074040080CF +:1005A40034040080740400807404008074040080A7 +:1005B4004404008074040080740400807404008087 +:1005C4005404008074040080740400807404008067 +:0405D400640400803B :040000058000000077 :00000001FF diff --git a/src/main/c/emulator/src/main.c b/src/main/c/emulator/src/main.c index 36090c7..aa058f7 100755 --- a/src/main/c/emulator/src/main.c +++ b/src/main/c/emulator/src/main.c @@ -4,11 +4,11 @@ extern const unsigned int _sp; extern void trapEntry(); +extern void emulationTrap(); void init() { - csr_write(mtvec, trapEntry); - unsigned int sp = (unsigned int) (&_sp); + csr_write(mtvec, trapEntry); csr_write(mscratch, sp -32*4); csr_write(mstatus, 0x0800); csr_write(mepc, OS_CALL); @@ -39,6 +39,18 @@ void redirectTrap(){ csr_write(sbadaddr, csr_read(mbadaddr)); csr_write(sepc, csr_read(mepc)); csr_write(scause, csr_read(mcause)); + csr_write(mepc, csr_read(stvec)); +} + +void emulationTrapToSupervisorTrap(uint32_t sepc, uint32_t mstatus){ + csr_write(sbadaddr, csr_read(mbadaddr)); + csr_write(scause, csr_read(mcause)); + csr_write(sepc, sepc); + csr_write(mepc, csr_read(stvec)); + csr_clear(sstatus, MSTATUS_SPP); + csr_set(sstatus, (mstatus >> 3) & MSTATUS_SPP); + csr_clear(mstatus, MSTATUS_MPP); + csr_set(mstatus, 0x8000); } #define max(a,b) \ @@ -52,6 +64,61 @@ void redirectTrap(){ __typeof__ (b) _b = (b); \ _a < _b ? _a : _b; }) + + +//Will modify MEPC +int readWord(int address, int *data){ + int result, tmp; + int failed; + __asm__ __volatile__ ( + " li %[tmp], 0x00020000\n" + " csrs mstatus, %[tmp]\n" + " la %[tmp], 1f\n" + " csrw mepc, %[tmp]\n" + " li %[failed], 1\n" + " lw %[result], 0(%[address])\n" + " li %[failed], 0\n" + "1:\n" + " li %[tmp], 0x00020000\n" + " csrc mstatus, %[tmp]\n" + : [result]"=&r" (result), [failed]"=&r" (failed), [tmp]"=&r" (tmp) + : [address]"r" (address) + : "memory" + ); + + *data = result; + return failed; +} + +//Will modify MEPC +int writeWord(uint32_t address, uint32_t data){ + int result, tmp; + int failed; + __asm__ __volatile__ ( + " li %[tmp], 0x00020000\n" + " csrs mstatus, %[tmp]\n" + " la %[tmp], 1f\n" + " csrw mepc, %[tmp]\n" + " li %[failed], 1\n" + " sw %[data], 0(%[address])\n" + " li %[failed], 0\n" + "1:\n" + " li %[tmp], 0x00020000\n" + " csrc mstatus, %[tmp]\n" + : [failed]"=&r" (failed), [tmp]"=&r" (tmp) + : [address]"r" (address), [data]"r" (data) + : "memory" + ); + + return failed; +} + + + + + + + void trap(){ int cause = csr_read(mcause); if(cause < 0){ @@ -59,6 +126,8 @@ void trap(){ } else { switch(cause){ case CAUSE_ILLEGAL_INSTRUCTION:{ + int mepc = csr_read(mepc); + int mstatus = csr_read(mstatus); int instruction = csr_read(mbadaddr); int opcode = instruction & 0x7F; int funct3 = (instruction >> 12) & 0x7; @@ -67,10 +136,14 @@ void trap(){ switch(funct3){ case 0x2:{ int sel = instruction >> 27; - int*addr = (int*)readRegister((instruction >> 15) & 0x1F); + int addr = readRegister((instruction >> 15) & 0x1F); int src = readRegister((instruction >> 20) & 0x1F); int rd = (instruction >> 7) & 0x1F; - int readValue = *addr; + int readValue; + if(readWord(addr, &readValue)){ + emulationTrapToSupervisorTrap(mepc, mstatus); + return; + } int writeValue; switch(sel){ case 0x0: writeValue = src + readValue; break; @@ -85,8 +158,11 @@ void trap(){ default: redirectTrap(); return; break; } writeRegister(rd, readValue); - *addr = writeValue; - csr_write(mepc, csr_read(mepc) + 4); + if(writeWord(addr, writeValue)){ + emulationTrapToSupervisorTrap(mepc, mstatus); + return; + } + csr_write(mepc, mepc + 4); }break; default: redirectTrap(); break; } diff --git a/src/main/c/emulator/src/trap.S b/src/main/c/emulator/src/trap.S index 4746c22..4384d34 100644 --- a/src/main/c/emulator/src/trap.S +++ b/src/main/c/emulator/src/trap.S @@ -69,3 +69,5 @@ trapEntry: lw x31, 31*4(sp) csrrw sp, mscratch, sp mret + + diff --git a/src/main/scala/vexriscv/plugin/MmuPlugin.scala b/src/main/scala/vexriscv/plugin/MmuPlugin.scala index cc98e10..56a4f26 100644 --- a/src/main/scala/vexriscv/plugin/MmuPlugin.scala +++ b/src/main/scala/vexriscv/plugin/MmuPlugin.scala @@ -110,7 +110,13 @@ class MmuPlugin(virtualRange : UInt => Bool, val requireMmuLockup = virtualRange(port.bus.cmd.virtualAddress) && !port.bus.cmd.bypassTranslation && csr.satp.mode if(!allowMachineModeMmu) { requireMmuLockup clearWhen(!csr.status.mprv && privilegeService.isMachine()) - if(port.priority != MmuPort.PRIORITY_DATA) requireMmuLockup clearWhen(csr.status.mprv && pipeline(config.MPP) === 3) + when(privilegeService.isMachine()) { + if (port.priority == MmuPort.PRIORITY_DATA) { + requireMmuLockup clearWhen (!csr.status.mprv) + } else { + requireMmuLockup := False + } + } } when(requireMmuLockup) { diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index f5832ce..3b4953b 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -256,7 +256,8 @@ public: uint32_t spp : 1; uint32_t _3 : 2; uint32_t mpp : 2; - uint32_t _4 : 5; + uint32_t _4 : 4; + uint32_t mprv : 1; uint32_t sum : 1; uint32_t mxr : 1; }; @@ -412,7 +413,8 @@ public: enum AccessKind {READ,WRITE,EXECUTE}; bool v2p(uint32_t v, uint32_t *p, AccessKind kind){ - if(privilege == 3 || satp.mode == 0){ + uint32_t effectivePrivilege = status.mprv && kind != EXECUTE ? status.mpp : privilege; + if(effectivePrivilege == 3 || satp.mode == 0){ *p = v; } else { Tlb tlb; @@ -424,8 +426,8 @@ public: if(!tlb.v) return true; superPage = false; } - if(!tlb.u && privilege == 0) return true; - if( tlb.u && privilege == 1 && !status.sum) return true; + if(!tlb.u && effectivePrivilege == 0) return true; + if( tlb.u && effectivePrivilege == 1 && !status.sum) return true; if(superPage && tlb.ppn0 != 0) return true; switch(kind){ case READ: if(!tlb.r && !(status.mxr && tlb.x)) return true; break; diff --git a/src/test/scala/vexriscv/experimental/PlicCost.scala b/src/test/scala/vexriscv/experimental/PlicCost.scala index 6f044e6..79d5c66 100644 --- a/src/test/scala/vexriscv/experimental/PlicCost.scala +++ b/src/test/scala/vexriscv/experimental/PlicCost.scala @@ -40,9 +40,9 @@ class PlicBench(inputCount : Int) extends Component{ io.cpuInterrupt := targets(0).iep val plicMapping = PlicMapping.light.copy( - // gatewayPriorityReadGen = true, - // gatewayPendingReadGen = true, - // targetThresholdReadGen = true +// gatewayPriorityReadGen = true, +// gatewayPendingReadGen = true, +// targetThresholdReadGen = true ) gateways.foreach(_.priority := 1)