diff --git a/README.md b/README.md
index 22bfba8..bb37f03 100644
--- a/README.md
+++ b/README.md
@@ -57,7 +57,7 @@ For commercial support, please contact spinalhdl@gmail.com.
 
 ## Area usage and maximal frequency
 
-The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral).<br>
+The following numbers were obtained by synthesizing the CPU as toplevel on the fastest speed grade without any specific synthesis options to save area or to get better maximal frequency (neutral).<br>
 The clock constraint is set to an unattainable value, which tends to increase the design area.<br>
 The dhrystone benchmark was compiled with the `-O3 -fno-inline` option.<br>
 All the cached configurations have some cache trashing during the dhrystone benchmark except the `VexRiscv full max perf` one. This, of course, reduces the performance. It is possible to produce
@@ -824,6 +824,12 @@ This plugin implements the register file.
 
 This register file use a `don't care` read-during-write policy, so the bypassing/hazard plugin should take care of this.
 
+If you get a `Missing inserts : INSTRUCTION_ANTICIPATE` error, that's because the RegFilePlugin is configured to use SYNC memory read ports to access the register file, but the IBus plugin configuration can't provide the instruction's register file read address one cycle before the decode stage. To workaround that you can :
+
+- Configure the RegFilePlugin to implement the register file read in a asyncronus manner (ASYNC), if your target device support such things
+- If you use the IBusSimplePlugin, you need to enable the injectorStage configuration
+- If you use the IBusCachedPlugin, you can either enable the injectorStage, or set twoCycleCache + twoCycleRam to false.
+
 #### HazardSimplePlugin
 
 This plugin checks the pipeline instruction dependencies and, if necessary or possible, will stop the instruction in the decoding stage or bypass the instruction results
diff --git a/src/main/c/emulator/makefile b/src/main/c/emulator/makefile
index 7534d08..6f3c8fc 100755
--- a/src/main/c/emulator/makefile
+++ b/src/main/c/emulator/makefile
@@ -18,10 +18,11 @@ sim: all
 qemu: CFLAGS += -DQEMU
 qemu: all
 
-litex: CFLAGS += -DLITEX -I${LITEX_BASE}/software/include
-litex: | check_litex_base all
-check_litex_base:
+litex: CFLAGS += -DLITEX -I${LITEX_GENERATED} -I${LITEX_BASE}/litex/soc/software/include
+litex: | check_litex all
+check_litex:
 	@[ "${LITEX_BASE}" ] || ( echo ">> LITEX_BASE is not set"; exit 1 )
+	@[ "${LITEX_GENERATED}" ] || ( echo ">> LITEX_GENERATED is not set"; exit 1 )
 
 include ${STANDALONE}/common/riscv64-unknown-elf.mk
 include ${STANDALONE}/common/standalone.mk
diff --git a/src/main/c/emulator/src/hal.c b/src/main/c/emulator/src/hal.c
index 5a151bb..aa6745b 100644
--- a/src/main/c/emulator/src/hal.c
+++ b/src/main/c/emulator/src/hal.c
@@ -146,38 +146,6 @@ void halInit(){
 
 #ifdef LITEX
 
-// this is copied from LiteX <hw/common.h>
-#define CSR_ACCESSORS_DEFINED
-static inline void csr_writeb(uint8_t value, unsigned long addr)
-{
-	*((volatile uint8_t *)addr) = value;
-}
-
-static inline uint8_t csr_readb(unsigned long addr)
-{
-	return *(volatile uint8_t *)addr;
-}
-
-static inline void csr_writew(uint16_t value, unsigned long addr)
-{
-	*((volatile uint16_t *)addr) = value;
-}
-
-static inline uint16_t csr_readw(unsigned long addr)
-{
-	return *(volatile uint16_t *)addr;
-}
-
-static inline void csr_writel(uint32_t value, unsigned long addr)
-{
-	*((volatile uint32_t *)addr) = value;
-}
-
-static inline uint32_t csr_readl(unsigned long addr)
-{
-	return *(volatile uint32_t *)addr;
-}
-
 // this is a file generated by LiteX
 #include <generated/csr.h>
 
diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
index 93e65e3..c04d167 100644
--- a/src/main/scala/vexriscv/plugin/DebugPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
@@ -213,18 +213,17 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount :
         iBusFetcher.haltIt()
       }
 
-      when(stepIt) {
-        //Assume nothing will stop the CPU in the decode stage
+      when(stepIt && iBusFetcher.incoming()) {
+        iBusFetcher.haltIt()
         when(decode.arbitration.isValid) {
           haltIt := True
-          decode.arbitration.flushNext := True
         }
       }
 
       //Avoid having two C instruction executed in a single step
       if(pipeline(RVC_GEN)){
         val cleanStep = RegNext(stepIt && decode.arbitration.isFiring) init(False)
-        decode.arbitration.removeIt setWhen(cleanStep)
+        execute.arbitration.flushNext setWhen(cleanStep)
       }
 
       io.resetOut := RegNext(resetIt)