From 5aa0b86d9697b6ab617966cbf6b0fbdb752d4418 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 7 Apr 2020 12:13:40 +0200 Subject: [PATCH 1/4] Fix DebugPlugin step by step --- src/main/scala/vexriscv/plugin/DebugPlugin.scala | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala index 93e65e3..c04d167 100644 --- a/src/main/scala/vexriscv/plugin/DebugPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala @@ -213,18 +213,17 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount : iBusFetcher.haltIt() } - when(stepIt) { - //Assume nothing will stop the CPU in the decode stage + when(stepIt && iBusFetcher.incoming()) { + iBusFetcher.haltIt() when(decode.arbitration.isValid) { haltIt := True - decode.arbitration.flushNext := True } } //Avoid having two C instruction executed in a single step if(pipeline(RVC_GEN)){ val cleanStep = RegNext(stepIt && decode.arbitration.isFiring) init(False) - decode.arbitration.removeIt setWhen(cleanStep) + execute.arbitration.flushNext setWhen(cleanStep) } io.resetOut := RegNext(resetIt) From f20eb4d5413efc663c6882ad5ea7877b140b5dd1 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 18 Mar 2020 12:02:27 +0100 Subject: [PATCH 2/4] Merge pull request #115 from antmicro/fix_emulator emulator: Use external hw/common.h from LiteX --- src/main/c/emulator/makefile | 7 ++++--- src/main/c/emulator/src/hal.c | 32 -------------------------------- 2 files changed, 4 insertions(+), 35 deletions(-) diff --git a/src/main/c/emulator/makefile b/src/main/c/emulator/makefile index 7534d08..6f3c8fc 100755 --- a/src/main/c/emulator/makefile +++ b/src/main/c/emulator/makefile @@ -18,10 +18,11 @@ sim: all qemu: CFLAGS += -DQEMU qemu: all -litex: CFLAGS += -DLITEX -I${LITEX_BASE}/software/include -litex: | check_litex_base all -check_litex_base: +litex: CFLAGS += -DLITEX -I${LITEX_GENERATED} -I${LITEX_BASE}/litex/soc/software/include +litex: | check_litex all +check_litex: @[ "${LITEX_BASE}" ] || ( echo ">> LITEX_BASE is not set"; exit 1 ) + @[ "${LITEX_GENERATED}" ] || ( echo ">> LITEX_GENERATED is not set"; exit 1 ) include ${STANDALONE}/common/riscv64-unknown-elf.mk include ${STANDALONE}/common/standalone.mk diff --git a/src/main/c/emulator/src/hal.c b/src/main/c/emulator/src/hal.c index 5a151bb..aa6745b 100644 --- a/src/main/c/emulator/src/hal.c +++ b/src/main/c/emulator/src/hal.c @@ -146,38 +146,6 @@ void halInit(){ #ifdef LITEX -// this is copied from LiteX -#define CSR_ACCESSORS_DEFINED -static inline void csr_writeb(uint8_t value, unsigned long addr) -{ - *((volatile uint8_t *)addr) = value; -} - -static inline uint8_t csr_readb(unsigned long addr) -{ - return *(volatile uint8_t *)addr; -} - -static inline void csr_writew(uint16_t value, unsigned long addr) -{ - *((volatile uint16_t *)addr) = value; -} - -static inline uint16_t csr_readw(unsigned long addr) -{ - return *(volatile uint16_t *)addr; -} - -static inline void csr_writel(uint32_t value, unsigned long addr) -{ - *((volatile uint32_t *)addr) = value; -} - -static inline uint32_t csr_readl(unsigned long addr) -{ - return *(volatile uint32_t *)addr; -} - // this is a file generated by LiteX #include From 6e239fb2808743134108b159559584dbb36e169c Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 20 Mar 2020 11:26:38 +0100 Subject: [PATCH 3/4] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 22bfba8..84b811e 100644 --- a/README.md +++ b/README.md @@ -57,7 +57,7 @@ For commercial support, please contact spinalhdl@gmail.com. ## Area usage and maximal frequency -The following numbers were obtained by synthesizing the CPU as toplevel without any specific synthesis options to save area or to get better maximal frequency (neutral).
+The following numbers were obtained by synthesizing the CPU as toplevel on the fastest speed grade without any specific synthesis options to save area or to get better maximal frequency (neutral).
The clock constraint is set to an unattainable value, which tends to increase the design area.
The dhrystone benchmark was compiled with the `-O3 -fno-inline` option.
All the cached configurations have some cache trashing during the dhrystone benchmark except the `VexRiscv full max perf` one. This, of course, reduces the performance. It is possible to produce From 5eaa5ba4db17b967549c669afcc20a74aebc47e8 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 28 Mar 2020 15:38:32 +0100 Subject: [PATCH 4/4] Update README.md --- README.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/README.md b/README.md index 84b811e..bb37f03 100644 --- a/README.md +++ b/README.md @@ -824,6 +824,12 @@ This plugin implements the register file. This register file use a `don't care` read-during-write policy, so the bypassing/hazard plugin should take care of this. +If you get a `Missing inserts : INSTRUCTION_ANTICIPATE` error, that's because the RegFilePlugin is configured to use SYNC memory read ports to access the register file, but the IBus plugin configuration can't provide the instruction's register file read address one cycle before the decode stage. To workaround that you can : + +- Configure the RegFilePlugin to implement the register file read in a asyncronus manner (ASYNC), if your target device support such things +- If you use the IBusSimplePlugin, you need to enable the injectorStage configuration +- If you use the IBusCachedPlugin, you can either enable the injectorStage, or set twoCycleCache + twoCycleRam to false. + #### HazardSimplePlugin This plugin checks the pipeline instruction dependencies and, if necessary or possible, will stop the instruction in the decoding stage or bypass the instruction results