From 206c7ca638f94752a42a74138472c177151c9516 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Fri, 24 May 2019 00:22:58 +0200 Subject: [PATCH] Fix Bmb datacache bridge --- src/main/scala/vexriscv/ip/DataCache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala index d34fceb..9239cf5 100644 --- a/src/main/scala/vexriscv/ip/DataCache.scala +++ b/src/main/scala/vexriscv/ip/DataCache.scala @@ -323,7 +323,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave bus.cmd.opcode := (cmd.wr ? B(Bmb.Cmd.Opcode.WRITE) | B(Bmb.Cmd.Opcode.READ)) bus.cmd.address := cmd.address.resized bus.cmd.data := cmd.data - bus.cmd.length := cmd.length << 2 //TODO better sub word access + bus.cmd.length := (cmd.length << 2) | 3 //TODO better sub word access bus.cmd.mask := cmd.mask cmd.ready := bus.cmd.ready