diff --git a/src/main/scala/vexriscv/demo/Linux.scala b/src/main/scala/vexriscv/demo/Linux.scala
index 0d6fe55..31e9198 100644
--- a/src/main/scala/vexriscv/demo/Linux.scala
+++ b/src/main/scala/vexriscv/demo/Linux.scala
@@ -88,7 +88,6 @@ https://github.com/riscv/riscv-qemu/wiki#build-and-install
 */
 
 
-//TODO have to check, look like supervisor can't get interrupt if the machine mod didn't delegated it, have to check exactly
 object LinuxGen {
   def configFull(litex : Boolean, withMmu : Boolean) = {
     val config = VexRiscvConfig(