diff --git a/src/main/scala/vexriscv/demo/VexRiscvAxi4Linux.scala b/src/main/scala/vexriscv/demo/VexRiscvAxi4Linux.scala
new file mode 100644
index 0000000..ff2ff11
--- /dev/null
+++ b/src/main/scala/vexriscv/demo/VexRiscvAxi4Linux.scala
@@ -0,0 +1,157 @@
+package vexriscv.demo
+
+import spinal.core._
+import spinal.lib._
+import spinal.lib.bus.amba4.axi.Axi4ReadOnly
+import spinal.lib.com.jtag.Jtag
+import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag}
+import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
+import vexriscv.plugin._
+import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin}
+
+
+object VexRiscvAxi4Linux{
+  def main(args: Array[String]) {
+    val report = SpinalVerilog{
+
+      //CPU configuration
+      val cpuConfig = VexRiscvConfig(
+        plugins = List(
+          new PcManagerSimplePlugin(0x00000000l, false),
+          new IBusCachedPlugin(
+            prediction = STATIC,
+            config = InstructionCacheConfig(
+              cacheSize = 4096,
+              bytePerLine = 64,
+              wayCount = 1,
+              addressWidth = 32,
+              cpuDataWidth = 32,
+              memDataWidth = 32,
+              catchIllegalAccess = true,
+              catchAccessFault = true,
+              asyncTagMemory = false,
+              twoCycleRam = true,
+              twoCycleCache = true
+            ),
+            memoryTranslatorPortConfig = MmuPortConfig(
+              portTlbSize = 4,
+              latency = 1,
+              earlyRequireMmuLockup = true,
+              earlyCacheHits = true
+            )
+          ),
+          new DBusCachedPlugin(
+            config = new DataCacheConfig(
+              cacheSize         = 4096,
+              bytePerLine       = 64,
+              wayCount          = 1,
+              addressWidth      = 32,
+              cpuDataWidth      = 32,
+              memDataWidth      = 32,
+              catchAccessError  = true,
+              catchIllegal      = true,
+              catchUnaligned    = true,
+              withLrSc = true,
+              withAmo = true
+            ),
+            memoryTranslatorPortConfig = MmuPortConfig(
+              portTlbSize = 4,
+              latency = 1,
+              earlyRequireMmuLockup = true,
+              earlyCacheHits = true
+            )
+          ),
+          new MmuPlugin(
+            ioRange      = _(31 downto 28) === 0xF
+          ),
+          new DecoderSimplePlugin(
+            catchIllegalInstruction = true
+          ),
+          new RegFilePlugin(
+            regFileReadyKind = plugin.SYNC,
+            zeroBoot = false
+          ),
+          new IntAluPlugin,
+          new SrcPlugin(
+            separatedAddSub = false,
+            executeInsertion = true
+          ),
+          new FullBarrelShifterPlugin,
+          new MulPlugin,
+          new DivPlugin,
+          new HazardSimplePlugin(
+            bypassExecute           = true,
+            bypassMemory            = true,
+            bypassWriteBack         = true,
+            bypassWriteBackBuffer   = true,
+            pessimisticUseSrc       = false,
+            pessimisticWriteRegFile = false,
+            pessimisticAddressMatch = false
+          ),
+          new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
+          new BranchPlugin(
+            earlyBranch = false,
+            catchAddressMisaligned = true
+          ),
+          new CsrPlugin(CsrPluginConfig.openSbi(mhartid = 0, misa = Riscv.misaToInt(s"ima")).copy(utimeAccess = CsrAccess.READ_ONLY)),
+          new YamlPlugin("cpu0.yaml")
+        )
+      )
+
+      //CPU instanciation
+      val cpu = new VexRiscv(cpuConfig)
+
+      //CPU modifications to be an Avalon one
+      cpu.setDefinitionName("VexRiscvAxi4")
+      cpu.rework {
+        var iBus : Axi4ReadOnly = null
+        for (plugin <- cpuConfig.plugins) plugin match {
+          case plugin: IBusSimplePlugin => {
+            plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
+            iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig())
+              .setName("iBusAxi")
+              .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
+          }
+          case plugin: IBusCachedPlugin => {
+            plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
+            iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig())
+              .setName("iBusAxi")
+              .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
+          }
+          case plugin: DBusSimplePlugin => {
+            plugin.dBus.setAsDirectionLess()
+            master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig())
+              .setName("dBusAxi")
+              .addTag(ClockDomainTag(ClockDomain.current))
+          }
+          case plugin: DBusCachedPlugin => {
+            plugin.dBus.setAsDirectionLess()
+            master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig())
+              .setName("dBusAxi")
+              .addTag(ClockDomainTag(ClockDomain.current))
+          }
+          case plugin: DebugPlugin => plugin.debugClockDomain {
+            plugin.io.bus.setAsDirectionLess()
+            val jtag = slave(new Jtag())
+              .setName("jtag")
+            jtag <> plugin.io.bus.fromJtag()
+            plugin.io.resetOut
+              .addTag(ResetEmitterTag(plugin.debugClockDomain))
+              .parent = null //Avoid the io bundle to be interpreted as a QSys conduit
+          }
+          case _ =>
+        }
+        for (plugin <- cpuConfig.plugins) plugin match {
+          case plugin: CsrPlugin => {
+            plugin.externalInterrupt
+              .addTag(InterruptReceiverTag(iBus, ClockDomain.current))
+            plugin.timerInterrupt
+              .addTag(InterruptReceiverTag(iBus, ClockDomain.current))
+          }
+          case _ =>
+        }
+      }
+      cpu
+    }
+  }
+}