From 2504f9b9b971ed987ef271f308f8f3b789d5e9e3 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 10 Nov 2022 15:49:03 +0100 Subject: [PATCH] RISC-V debug havereset implemented --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 54d805f..4d7d708 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -696,6 +696,10 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep bus.running := running bus.halted := !running bus.unavailable := RegNext(ClockDomain.current.isResetActive) + + val reseting = RegNext(False) init(True) + bus.haveReset := RegInit(False) setWhen(reseting) clearWhen(bus.ackReset) + val enterHalt = running.getAheadValue().fall(False) val doHalt = RegInit(False) setWhen(bus.haltReq && bus.running && !debugMode) clearWhen(enterHalt)