From 25d880f6c7f30fea5e6f3393eba9b2360ab71fa1 Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Fri, 28 Feb 2020 18:20:08 +0100
Subject: [PATCH] Fix synthesis bench

---
 src/main/scala/vexriscv/demo/SynthesisBench.scala | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala
index 4df6f5e..91c1e5f 100644
--- a/src/main/scala/vexriscv/demo/SynthesisBench.scala
+++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala
@@ -4,8 +4,9 @@ import spinal.core._
 import spinal.lib._
 import spinal.lib.eda.bench._
 import spinal.lib.eda.icestorm.IcestormStdTargets
+import spinal.lib.io.InOutWrapper
 import vexriscv.VexRiscv
-import vexriscv.plugin.{DecoderSimplePlugin}
+import vexriscv.plugin.DecoderSimplePlugin
 
 import scala.collection.mutable.ArrayBuffer
 import scala.util.Random
@@ -132,7 +133,7 @@ object BrieySynthesisBench {
       override def getName(): String = "Briey"
       override def getRtlPath(): String = "Briey.v"
       SpinalVerilog({
-        val briey = new Briey(BrieyConfig.default).setDefinitionName(getRtlPath().split("\\.").head)
+        val briey = InOutWrapper(new Briey(BrieyConfig.default).setDefinitionName(getRtlPath().split("\\.").head))
         briey.io.axiClk.setName("clk")
         briey
       })
@@ -161,7 +162,7 @@ object MuraxSynthesisBench {
       override def getName(): String = "Murax"
       override def getRtlPath(): String = "Murax.v"
       SpinalVerilog({
-        val murax = new Murax(MuraxConfig.default.copy(gpioWidth = 8)).setDefinitionName(getRtlPath().split("\\.").head)
+        val murax = InOutWrapper(new Murax(MuraxConfig.default.copy(gpioWidth = 8)).setDefinitionName(getRtlPath().split("\\.").head))
         murax.io.mainClk.setName("clk")
         murax
       })
@@ -172,7 +173,7 @@ object MuraxSynthesisBench {
       override def getName(): String = "MuraxFast"
       override def getRtlPath(): String = "MuraxFast.v"
       SpinalVerilog({
-        val murax = new Murax(MuraxConfig.fast.copy(gpioWidth = 8)).setDefinitionName(getRtlPath().split("\\.").head)
+        val murax = InOutWrapper(new Murax(MuraxConfig.fast.copy(gpioWidth = 8)).setDefinitionName(getRtlPath().split("\\.").head))
         murax.io.mainClk.setName("clk")
         murax
       })