From 2b6f43cef87dce8cc52e59fd09655f30cb931a95 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 23 Feb 2018 19:16:31 +0100 Subject: [PATCH] Fix Murax memory mapping range --- src/main/scala/vexriscv/demo/Murax.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index bca9cf5..2ccff01 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -278,7 +278,7 @@ case class Murax(config : MuraxConfig) extends Component{ val logic = new MuraxSimpleBusDecoder( master = mainBusArbiter.io.masterBus, specification = List[(SimpleBus,SizeMapping)]( - ram.io.bus -> (0x80000000l, onChipRamSize kB), + ram.io.bus -> (0x80000000l, onChipRamSize), apbBridge.io.simpleBus -> (0xF0000000l, 1 MB) ), pipelineMaster = pipelineMainBus