diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala
index f692680..591e36e 100644
--- a/src/main/scala/vexriscv/ip/DataCache.scala
+++ b/src/main/scala/vexriscv/ip/DataCache.scala
@@ -184,16 +184,17 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
     slave(rsp)
   }
 
-  def toAxi4Shared(stageCmd : Boolean = false): Axi4Shared = {
+  def toAxi4Shared(stageCmd : Boolean = false, pendingWritesMax  : Int = 7): Axi4Shared = {
     val axi = Axi4Shared(p.getAxi4SharedConfig())
-    val pendingWritesMax = 7
+
+    val cmdPreFork = if (stageCmd) cmd.stage.stage().s2mPipe() else cmd
+
     val pendingWrites = CounterUpDown(
       stateCount = pendingWritesMax + 1,
-      incWhen = axi.sharedCmd.fire && axi.sharedCmd.write,
+      incWhen = cmdPreFork.fire && cmdPreFork.wr,
       decWhen = axi.writeRsp.fire
     )
 
-    val cmdPreFork = if (stageCmd) cmd.stage.stage().s2mPipe() else cmd
     val hazard = (pendingWrites =/= 0 && !cmdPreFork.wr) || pendingWrites === pendingWritesMax
     val (cmdFork, dataFork) = StreamFork2(cmdPreFork.haltWhen(hazard))
     val cmdStage  = cmdFork.throwWhen(RegNextWhen(!cmdFork.last,cmdFork.fire).init(False))
diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
index fe5ac77..e08b640 100644
--- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
@@ -106,17 +106,19 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
     s
   }
 
-  def toAxi4Shared(stageCmd : Boolean = false): Axi4Shared = {
+  def toAxi4Shared(stageCmd : Boolean = false, pendingWritesMax : Int = 7): Axi4Shared = {
     val axi = Axi4Shared(DBusSimpleBus.getAxi4Config())
-    val pendingWritesMax = 7
+
+    val cmdPreFork = if (stageCmd) cmd.stage.stage().s2mPipe() else cmd
+
     val pendingWrites = CounterUpDown(
       stateCount = pendingWritesMax + 1,
-      incWhen = axi.sharedCmd.fire && axi.sharedCmd.write,
+      incWhen = cmdPreFork.fire && cmdPreFork.wr,
       decWhen = axi.writeRsp.fire
     )
 
-    val cmdPreFork = if (stageCmd) cmd.stage.stage().s2mPipe() else cmd
-    val (cmdFork, dataFork) = StreamFork2(cmdPreFork.haltWhen((pendingWrites =/= 0 && cmdPreFork.valid && !cmdPreFork.wr) || pendingWrites === pendingWritesMax))
+    val hazard = (pendingWrites =/= 0 && cmdPreFork.valid && !cmdPreFork.wr) || pendingWrites === pendingWritesMax
+    val (cmdFork, dataFork) = StreamFork2(cmdPreFork.haltWhen(hazard))
     axi.sharedCmd.arbitrationFrom(cmdFork)
     axi.sharedCmd.write := cmdFork.wr
     axi.sharedCmd.prot := "010"