From 2c6889e688cdfc54adea86e3edd69dae3b9fea2b Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Thu, 10 Aug 2017 22:47:57 +0200 Subject: [PATCH] Murax mainBus now handle unmapped memory access allowing the debug to access unmapped area without locking the CPU Murax add dhrystone config --- src/main/scala/vexriscv/demo/Murax.scala | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index e977a91..ec6b4cd 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -397,11 +397,13 @@ case class Murax(config : MuraxConfig) extends Component{ slaveBus.cmd.payload := masterBus.cmd.payload hit } - masterBus.cmd.ready := (hits,slaveBuses).zipped.map(_ && _.cmd.ready).orR + val noHit = !hits.orR + masterBus.cmd.ready := (hits,slaveBuses).zipped.map(_ && _.cmd.ready).orR || noHit - val rspPending = RegInit(False) clearWhen(masterBus.rsp.valid) setWhen(masterBus.cmd.fire && !masterBus.cmd.wr) + val rspPending = RegInit(False) clearWhen(masterBus.rsp.valid) setWhen(masterBus.cmd.fire && !masterBus.cmd.wr) + val rspNoHit = RegNext(False) init(False) setWhen(noHit) val rspSourceId = RegNextWhen(OHToUInt(hits), masterBus.cmd.fire) - masterBus.rsp.valid := slaveBuses.map(_.rsp.valid).orR + masterBus.rsp.valid := slaveBuses.map(_.rsp.valid).orR || (rspPending && rspNoHit) masterBus.rsp.payload := slaveBuses.map(_.rsp.payload).read(rspSourceId) when(rspPending && !masterBus.rsp.valid) { //Only one pending read request is allowed @@ -466,10 +468,14 @@ case class Murax(config : MuraxConfig) extends Component{ object Murax{ def main(args: Array[String]) { SpinalVerilog(Murax(MuraxConfig.default)) -// SpinalVerilog(Murax(MuraxConfig.fast.copy(onChipRamSize = 256 kB))) //dhrystone config (more ram) } } +object MuraxDhrystoneReady{ + def main(args: Array[String]) { + SpinalVerilog(Murax(MuraxConfig.fast.copy(onChipRamSize = 256 kB))) + } +} //Will blink led and echo UART RX to UART TX (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin) object MuraxWithRamInit{