diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index 8db4316..9c223a7 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -26,29 +26,40 @@ import vexriscv.ip._ import spinal.lib.bus.avalon.AvalonMM import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag} + +//make clean all SEED=42 MMU=no STOP_ON_ERROR=yes SMP=yes SUPERVISOR=yes REDO=10 DHRYSTONE=no LRSC=yes LINUX_REGRESSION=yes TRACE=yes TRACE_START=1000000000000l FLOW_INFO=no object TestsWorkspace { def main(args: Array[String]) { def configFull = { val config = VexRiscvConfig( plugins = List( - // new IBusSimplePlugin( - // resetVector = 0x80000000l, - // cmdForkOnSecondStage = false, - // cmdForkPersistence = false, - // prediction = NONE, - // historyRamSizeLog2 = 10, - // catchAccessFault = false, - // compressedGen = false, - // busLatencyMin = 1, - // injectorStage = true - // ), + new MmuPlugin( + ioRange = x => x(31 downto 28) === 0xF + ), + //Uncomment the whole IBusSimplePlugin and comment IBusCachedPlugin if you want uncached iBus config + // new IBusSimplePlugin( + // resetVector = 0x80000000l, + // cmdForkOnSecondStage = false, + // cmdForkPersistence = false, + // prediction = DYNAMIC_TARGET, + // historyRamSizeLog2 = 10, + // catchAccessFault = true, + // compressedGen = true, + // busLatencyMin = 1, + // injectorStage = true, + // memoryTranslatorPortConfig = withMmu generate MmuPortConfig( + // portTlbSize = 4 + // ) + // ), + + //Uncomment the whole IBusCachedPlugin and comment IBusSimplePlugin if you want cached iBus config new IBusCachedPlugin( resetVector = 0x80000000l, compressedGen = false, - prediction = NONE, - injectorStage = true, + prediction = STATIC, + injectorStage = false, config = InstructionCacheConfig( - cacheSize = 4096, + cacheSize = 4096*1, bytePerLine = 32, wayCount = 1, addressWidth = 32, @@ -59,20 +70,28 @@ object TestsWorkspace { asyncTagMemory = false, twoCycleRam = false, twoCycleCache = true + // ) ), - memoryTranslatorPortConfig = MemoryTranslatorPortConfig( + memoryTranslatorPortConfig = MmuPortConfig( portTlbSize = 4 ) ), -// ).newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0 && a(5))), - // new DBusSimplePlugin( - // catchAddressMisaligned = true, - // catchAccessFault = false, - // earlyInjection = false - // ), + // ).newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0 && a(5))), + // new DBusSimplePlugin( + // catchAddressMisaligned = true, + // catchAccessFault = true, + // earlyInjection = false, + // withLrSc = true, + // memoryTranslatorPortConfig = withMmu generate MmuPortConfig( + // portTlbSize = 4 + // ) + // ), new DBusCachedPlugin( + dBusCmdMasterPipe = true, + dBusCmdSlavePipe = true, + dBusRspSlavePipe = true, config = new DataCacheConfig( - cacheSize = 4096, + cacheSize = 4096*1, bytePerLine = 32, wayCount = 1, addressWidth = 32, @@ -81,33 +100,34 @@ object TestsWorkspace { catchAccessError = true, catchIllegal = true, catchUnaligned = true, - withLrSc = true + withLrSc = true, + withAmo = false, + withSmp = true + // ) ), - // memoryTranslatorPortConfig = null - memoryTranslatorPortConfig = MemoryTranslatorPortConfig( - portTlbSize = 6 + memoryTranslatorPortConfig = MmuPortConfig( + portTlbSize = 4 ) ), - // new StaticMemoryTranslatorPlugin( + + // new MemoryTranslatorPlugin( + // tlbSize = 32, + // virtualRange = _(31 downto 28) === 0xC, // ioRange = _(31 downto 28) === 0xF // ), - new MemoryTranslatorPlugin( - tlbSize = 32, - virtualRange = _(31 downto 28) === 0xC, - ioRange = _(31 downto 28) === 0xF - ), + new DecoderSimplePlugin( catchIllegalInstruction = true ), new RegFilePlugin( - regFileReadyKind = plugin.ASYNC, + regFileReadyKind = plugin.SYNC, zeroBoot = true ), new IntAluPlugin, new SrcPlugin( separatedAddSub = false ), - new FullBarrelShifterPlugin(earlyInjection = true), + new FullBarrelShifterPlugin(earlyInjection = false), // new LightShifterPlugin, new HazardSimplePlugin( bypassExecute = true, @@ -128,7 +148,7 @@ object TestsWorkspace { divUnrollFactor = 1 ), // new DivPlugin, - new CsrPlugin(CsrPluginConfig.all(0x80000020l)), + new CsrPlugin(CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = false)), // new CsrPlugin(//CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = true)/* // CsrPluginConfig( // catchIllegalAccess = false, @@ -154,9 +174,9 @@ object TestsWorkspace { // )), new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new BranchPlugin( - earlyBranch = true, + earlyBranch = false, catchAddressMisaligned = true, - fenceiGenAsAJump = true + fenceiGenAsAJump = false ), new YamlPlugin("cpu0.yaml") ) diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala index af6f15c..758186a 100644 --- a/src/main/scala/vexriscv/ip/DataCache.scala +++ b/src/main/scala/vexriscv/ip/DataCache.scala @@ -175,6 +175,7 @@ case class DataCacheMemCmd(p : DataCacheConfig) extends Bundle{ val last = Bool } case class DataCacheMemRsp(p : DataCacheConfig) extends Bundle{ + val last = Bool() val data = Bits(p.memDataWidth bit) val error = Bool val exclusive = p.withSmp generate Bool() @@ -446,15 +447,18 @@ class DataCache(p : DataCacheConfig) extends Component{ io.cpu.execute.haltIt := False val rspSync = True + val rspLast = True + val memCmdSent = RegInit(False) setWhen (io.mem.cmd.ready) clearWhen (!io.cpu.writeBack.isStuck) val pending = withSmp generate new Area{ val counter = Reg(UInt(log2Up(pendingMax) + 1 bits)) init(0) - counter := counter + U(io.mem.cmd.fire && io.mem.cmd.last) - U(io.mem.rsp.valid) + counter := counter + U(io.mem.cmd.fire && io.mem.cmd.last) - U(io.mem.rsp.valid && io.mem.rsp.last) val full = RegNext(counter.msb) val last = counter === 1 io.cpu.execute.haltIt setWhen(full) - rspSync clearWhen(!last) + rspSync clearWhen(!last || !memCmdSent) + rspLast clearWhen(!last) } @@ -568,8 +572,15 @@ class DataCache(p : DataCacheConfig) extends Component{ } + val cpuWriteToCache = False + when(cpuWriteToCache){ + dataWriteCmd.valid setWhen(request.wr && waysHit) + dataWriteCmd.address := mmuRsp.physicalAddress(lineRange.high downto wordRange.low) + dataWriteCmd.data := requestDataBypass + dataWriteCmd.mask := mask + dataWriteCmd.way := waysHits + } - val memCmdSent = RegInit(False) setWhen (io.mem.cmd.ready) clearWhen (!io.cpu.writeBack.isStuck) io.cpu.redo := False io.cpu.writeBack.accessError := False io.cpu.writeBack.mmuException := io.cpu.writeBack.isValid && (if(catchIllegal) mmuRsp.exception || (!mmuRsp.allowWrite && request.wr) || (!mmuRsp.allowRead && (!request.wr || isAmo)) else False) @@ -579,14 +590,16 @@ class DataCache(p : DataCacheConfig) extends Component{ io.mem.cmd.valid := False io.mem.cmd.address.assignDontCare() io.mem.cmd.length.assignDontCare() - io.mem.cmd.last.assignDontCare() + io.mem.cmd.last := True io.mem.cmd.wr := request.wr io.mem.cmd.mask := mask io.mem.cmd.data := requestDataBypass if(withExternalLrSc) io.mem.cmd.exclusive := request.isLrsc || (if(withAmo) request.isAmo else False) + val bypassCache = mmuRsp.isIoAccess || (if(withExternalLrSc) request.isLrsc else False) + when(io.cpu.writeBack.isValid) { - when(mmuRsp.isIoAccess || (if(withExternalLrSc) request.isLrsc else False)) { + when(bypassCache) { val waitResponse = !request.wr if(withExternalLrSc) waitResponse setWhen(request.isLrsc) @@ -595,7 +608,6 @@ class DataCache(p : DataCacheConfig) extends Component{ io.mem.cmd.valid := !memCmdSent io.mem.cmd.address := mmuRsp.physicalAddress(tagRange.high downto wordRange.low) @@ U(0, wordRange.low bit) io.mem.cmd.length := 0 - io.mem.cmd.last := True if(withInternalLrSc) when(request.isLrsc && !lrSc.reserved){ io.mem.cmd.valid := False @@ -603,18 +615,12 @@ class DataCache(p : DataCacheConfig) extends Component{ } } otherwise { when(waysHit || request.wr && !isAmo) { //Do not require a cache refill ? - //Data cache update - dataWriteCmd.valid setWhen(request.wr && waysHit) - dataWriteCmd.address := mmuRsp.physicalAddress(lineRange.high downto wordRange.low) - dataWriteCmd.data := requestDataBypass - dataWriteCmd.mask := mask - dataWriteCmd.way := waysHits + cpuWriteToCache := True //Write through io.mem.cmd.valid setWhen(request.wr) io.mem.cmd.address := mmuRsp.physicalAddress(tagRange.high downto wordRange.low) @@ U(0, wordRange.low bit) io.mem.cmd.length := 0 - io.mem.cmd.last := True io.cpu.writeBack.haltIt clearWhen(!request.wr || io.mem.cmd.ready) if(withAmo) when(isAmo){ @@ -642,22 +648,29 @@ class DataCache(p : DataCacheConfig) extends Component{ io.mem.cmd.wr := False io.mem.cmd.address := mmuRsp.physicalAddress(tagRange.high downto lineRange.low) @@ U(0,lineRange.low bit) io.mem.cmd.length := p.burstLength-1 - io.mem.cmd.last := True loaderValid setWhen(io.mem.cmd.ready) } } } - when(mmuRsp.isIoAccess){ + when(bypassCache){ io.cpu.writeBack.data := io.mem.rsp.data if(catchAccessError) io.cpu.writeBack.accessError := io.mem.rsp.valid && io.mem.rsp.error } otherwise { io.cpu.writeBack.data := dataMux if(catchAccessError) io.cpu.writeBack.accessError := (waysHits & B(tagsReadRsp.map(_.error))) =/= 0 } + if(withLrSc) when(request.isLrsc && request.wr){ - io.cpu.writeBack.data := B(!lrSc.reserved || !io.mem.rsp.exclusive).resized + val success = CombInit(lrSc.reserved) + if(withExternalLrSc) success clearWhen(!io.mem.rsp.exclusive) + + io.cpu.writeBack.data := B(!success).resized + + if(withExternalLrSc) when(io.cpu.writeBack.isValid && io.mem.rsp.valid && rspSync && success && waysHit){ + cpuWriteToCache := True + } } if(withAmo) when(request.isAmo){ requestDataBypass := internalAmo.resultReg @@ -687,7 +700,7 @@ class DataCache(p : DataCacheConfig) extends Component{ val waysAllocator = Reg(Bits(wayCount bits)) init(1) val error = RegInit(False) - when(valid && io.mem.rsp.valid && rspSync){ + when(valid && io.mem.rsp.valid && rspLast){ dataWriteCmd.valid := True dataWriteCmd.address := baseAddress(lineRange) @@ counter dataWriteCmd.data := io.mem.rsp.data diff --git a/src/test/cpp/raw/lrsc/build/lrsc.asm b/src/test/cpp/raw/lrsc/build/lrsc.asm index 4ff24b4..a2ba4c7 100644 --- a/src/test/cpp/raw/lrsc/build/lrsc.asm +++ b/src/test/cpp/raw/lrsc/build/lrsc.asm @@ -5,7 +5,7 @@ build/lrsc.elf: file format elf32-littleriscv Disassembly of section .crt_section: 80000000 : -80000000: 04c0006f j 8000004c <_start> +80000000: 06c0006f j 8000006c <_start> 80000004: 00000013 nop 80000008: 00000013 nop 8000000c: 00000013 nop @@ -29,115 +29,152 @@ Disassembly of section .crt_section: 80000044: 341e9073 csrw mepc,t4 80000048: 30200073 mret -8000004c <_start>: -8000004c: 00100e13 li t3,1 -80000050: 10000537 lui a0,0x10000 -80000054: 06400593 li a1,100 -80000058: 06500613 li a2,101 -8000005c: 06600693 li a3,102 -80000060: 00d52023 sw a3,0(a0) # 10000000 -80000064: 18b5262f sc.w a2,a1,(a0) -80000068: 00100713 li a4,1 -8000006c: 14e61a63 bne a2,a4,800001c0 -80000070: 00052703 lw a4,0(a0) -80000074: 14e69663 bne a3,a4,800001c0 -80000078: 00200e13 li t3,2 -8000007c: 10000537 lui a0,0x10000 -80000080: 00450513 addi a0,a0,4 # 10000004 -80000084: 06700593 li a1,103 -80000088: 06800613 li a2,104 -8000008c: 06900693 li a3,105 -80000090: 00d52023 sw a3,0(a0) -80000094: 18b5262f sc.w a2,a1,(a0) -80000098: 00100713 li a4,1 -8000009c: 12e61263 bne a2,a4,800001c0 -800000a0: 00052703 lw a4,0(a0) -800000a4: 10e69e63 bne a3,a4,800001c0 -800000a8: 00300e13 li t3,3 -800000ac: 10000537 lui a0,0x10000 -800000b0: 00450513 addi a0,a0,4 # 10000004 -800000b4: 06700593 li a1,103 -800000b8: 06800613 li a2,104 -800000bc: 06900693 li a3,105 -800000c0: 18b5262f sc.w a2,a1,(a0) -800000c4: 00100713 li a4,1 -800000c8: 0ee61c63 bne a2,a4,800001c0 +8000004c : +8000004c: 200002b7 lui t0,0x20000 +80000050: 00001337 lui t1,0x1 +80000054: 02000393 li t2,32 + +80000058 : +80000058: 0002ae03 lw t3,0(t0) # 20000000 +8000005c: 006282b3 add t0,t0,t1 +80000060: fff38393 addi t2,t2,-1 +80000064: fe039ae3 bnez t2,80000058 +80000068: 00008067 ret + +8000006c <_start>: +8000006c: 00100e13 li t3,1 +80000070: 10000537 lui a0,0x10000 +80000074: 06400593 li a1,100 +80000078: 06500613 li a2,101 +8000007c: 06600693 li a3,102 +80000080: 00d52023 sw a3,0(a0) # 10000000 +80000084: 18b5262f sc.w a2,a1,(a0) +80000088: 00100713 li a4,1 +8000008c: 18e61863 bne a2,a4,8000021c +80000090: 00052703 lw a4,0(a0) +80000094: 18e69463 bne a3,a4,8000021c + +80000098 : +80000098: 00200e13 li t3,2 +8000009c: 10000537 lui a0,0x10000 +800000a0: 00450513 addi a0,a0,4 # 10000004 +800000a4: 06700593 li a1,103 +800000a8: 06800613 li a2,104 +800000ac: 06900693 li a3,105 +800000b0: 00d52023 sw a3,0(a0) +800000b4: 18b5262f sc.w a2,a1,(a0) +800000b8: 00100713 li a4,1 +800000bc: 16e61063 bne a2,a4,8000021c +800000c0: 00052703 lw a4,0(a0) +800000c4: 14e69c63 bne a3,a4,8000021c +800000c8: f85ff0ef jal ra,8000004c 800000cc: 00052703 lw a4,0(a0) -800000d0: 0ee69863 bne a3,a4,800001c0 -800000d4: 00400e13 li t3,4 +800000d0: 14e69663 bne a3,a4,8000021c + +800000d4 : +800000d4: 00300e13 li t3,3 800000d8: 10000537 lui a0,0x10000 -800000dc: 00850513 addi a0,a0,8 # 10000008 -800000e0: 06a00593 li a1,106 -800000e4: 06b00613 li a2,107 -800000e8: 06c00693 li a3,108 -800000ec: 00d52023 sw a3,0(a0) -800000f0: 100527af lr.w a5,(a0) -800000f4: 18b5262f sc.w a2,a1,(a0) -800000f8: 0cd79463 bne a5,a3,800001c0 -800000fc: 0c061263 bnez a2,800001c0 -80000100: 00052703 lw a4,0(a0) -80000104: 0ae59e63 bne a1,a4,800001c0 -80000108: 00500e13 li t3,5 -8000010c: 10000537 lui a0,0x10000 -80000110: 00850513 addi a0,a0,8 # 10000008 -80000114: 06d00593 li a1,109 -80000118: 06e00613 li a2,110 -8000011c: 06f00693 li a3,111 -80000120: 00d52023 sw a3,0(a0) -80000124: 18b5262f sc.w a2,a1,(a0) -80000128: 08060c63 beqz a2,800001c0 -8000012c: 00052703 lw a4,0(a0) -80000130: 08e69863 bne a3,a4,800001c0 -80000134: 00700e13 li t3,7 -80000138: 10000537 lui a0,0x10000 -8000013c: 01450513 addi a0,a0,20 # 10000014 -80000140: 07800593 li a1,120 -80000144: 07900613 li a2,121 -80000148: 07a00693 li a3,122 -8000014c: 01000e93 li t4,16 +800000dc: 00450513 addi a0,a0,4 # 10000004 +800000e0: 06700593 li a1,103 +800000e4: 06800613 li a2,104 +800000e8: 06900693 li a3,105 +800000ec: 18b5262f sc.w a2,a1,(a0) +800000f0: 00100713 li a4,1 +800000f4: 12e61463 bne a2,a4,8000021c +800000f8: 00052703 lw a4,0(a0) +800000fc: 12e69063 bne a3,a4,8000021c +80000100: f4dff0ef jal ra,8000004c +80000104: 00052703 lw a4,0(a0) +80000108: 10e69a63 bne a3,a4,8000021c -80000150 : -80000150: 00d52023 sw a3,0(a0) -80000154: 100527af lr.w a5,(a0) -80000158: 18b5262f sc.w a2,a1,(a0) -8000015c: 06d79263 bne a5,a3,800001c0 -80000160: 06061063 bnez a2,800001c0 -80000164: 00052703 lw a4,0(a0) -80000168: 04e59c63 bne a1,a4,800001c0 -8000016c: fffe8e93 addi t4,t4,-1 -80000170: 00450513 addi a0,a0,4 -80000174: 00358593 addi a1,a1,3 -80000178: 00360613 addi a2,a2,3 -8000017c: 00368693 addi a3,a3,3 -80000180: fc0e98e3 bnez t4,80000150 -80000184: 00900e13 li t3,9 +8000010c : +8000010c: 00400e13 li t3,4 +80000110: 10000537 lui a0,0x10000 +80000114: 00850513 addi a0,a0,8 # 10000008 +80000118: 06a00593 li a1,106 +8000011c: 06b00613 li a2,107 +80000120: 06c00693 li a3,108 +80000124: 00d52023 sw a3,0(a0) +80000128: 100527af lr.w a5,(a0) +8000012c: 18b5262f sc.w a2,a1,(a0) +80000130: 0ed79663 bne a5,a3,8000021c +80000134: 0e061463 bnez a2,8000021c +80000138: 00052703 lw a4,0(a0) +8000013c: 0ee59063 bne a1,a4,8000021c +80000140: f0dff0ef jal ra,8000004c +80000144: 00052703 lw a4,0(a0) +80000148: 0ce59a63 bne a1,a4,8000021c + +8000014c : +8000014c: 00500e13 li t3,5 +80000150: 10000537 lui a0,0x10000 +80000154: 00850513 addi a0,a0,8 # 10000008 +80000158: 06d00593 li a1,109 +8000015c: 06e00613 li a2,110 +80000160: 06f00693 li a3,111 +80000164: 00d52023 sw a3,0(a0) +80000168: 18b5262f sc.w a2,a1,(a0) +8000016c: 0a060863 beqz a2,8000021c +80000170: 00052703 lw a4,0(a0) +80000174: 0ae69463 bne a3,a4,8000021c +80000178: ed5ff0ef jal ra,8000004c +8000017c: 00052703 lw a4,0(a0) +80000180: 08e69e63 bne a3,a4,8000021c +80000184: 00700e13 li t3,7 80000188: 10000537 lui a0,0x10000 -8000018c: 10050513 addi a0,a0,256 # 10000100 -80000190: 07b00593 li a1,123 -80000194: 07c00613 li a2,124 -80000198: 07d00693 li a3,125 -8000019c: 00d52023 sw a3,0(a0) -800001a0: 100527af lr.w a5,(a0) -800001a4: 00000073 ecall -800001a8: 18b527af sc.w a5,a1,(a0) -800001ac: 00000713 li a4,0 -800001b0: 00e79863 bne a5,a4,800001c0 +8000018c: 01450513 addi a0,a0,20 # 10000014 +80000190: 07800593 li a1,120 +80000194: 07900613 li a2,121 +80000198: 07a00693 li a3,122 +8000019c: 01000e93 li t4,16 + +800001a0 : +800001a0: 00d52023 sw a3,0(a0) +800001a4: 100527af lr.w a5,(a0) +800001a8: 18b5262f sc.w a2,a1,(a0) +800001ac: 06d79863 bne a5,a3,8000021c +800001b0: 06061663 bnez a2,8000021c 800001b4: 00052703 lw a4,0(a0) -800001b8: 00e59463 bne a1,a4,800001c0 -800001bc: 0100006f j 800001cc +800001b8: 06e59263 bne a1,a4,8000021c +800001bc: fffe8e93 addi t4,t4,-1 +800001c0: 00450513 addi a0,a0,4 +800001c4: 00358593 addi a1,a1,3 +800001c8: 00360613 addi a2,a2,3 +800001cc: 00368693 addi a3,a3,3 +800001d0: fc0e98e3 bnez t4,800001a0 -800001c0 : -800001c0: f0100137 lui sp,0xf0100 -800001c4: f2410113 addi sp,sp,-220 # f00fff24 -800001c8: 01c12023 sw t3,0(sp) +800001d4 : +800001d4: 00900e13 li t3,9 +800001d8: 10000537 lui a0,0x10000 +800001dc: 10050513 addi a0,a0,256 # 10000100 +800001e0: 07b00593 li a1,123 +800001e4: 07c00613 li a2,124 +800001e8: 07d00693 li a3,125 +800001ec: 00d52023 sw a3,0(a0) +800001f0: 100527af lr.w a5,(a0) +800001f4: 00000073 ecall +800001f8: 18b527af sc.w a5,a1,(a0) +800001fc: 00000713 li a4,0 +80000200: 00e79e63 bne a5,a4,8000021c +80000204: 00052703 lw a4,0(a0) +80000208: 00e59a63 bne a1,a4,8000021c +8000020c: e41ff0ef jal ra,8000004c +80000210: 00052703 lw a4,0(a0) +80000214: 00e59463 bne a1,a4,8000021c +80000218: 0100006f j 80000228 -800001cc : -800001cc: f0100137 lui sp,0xf0100 -800001d0: f2010113 addi sp,sp,-224 # f00fff20 -800001d4: 00012023 sw zero,0(sp) -800001d8: 00000013 nop -800001dc: 00000013 nop -800001e0: 00000013 nop -800001e4: 00000013 nop -800001e8: 00000013 nop -800001ec: 00000013 nop +8000021c : +8000021c: f0100137 lui sp,0xf0100 +80000220: f2410113 addi sp,sp,-220 # f00fff24 +80000224: 01c12023 sw t3,0(sp) + +80000228 : +80000228: f0100137 lui sp,0xf0100 +8000022c: f2010113 addi sp,sp,-224 # f00fff20 +80000230: 00012023 sw zero,0(sp) +80000234: 00000013 nop +80000238: 00000013 nop +8000023c: 00000013 nop +80000240: 00000013 nop +80000244: 00000013 nop +80000248: 00000013 nop diff --git a/src/test/cpp/raw/lrsc/build/lrsc.hex b/src/test/cpp/raw/lrsc/build/lrsc.hex index 1c1cd4c..b0ee273 100644 --- a/src/test/cpp/raw/lrsc/build/lrsc.hex +++ b/src/test/cpp/raw/lrsc/build/lrsc.hex @@ -1,34 +1,40 @@ :0200000480007A -:100000006F00C00413000000130000001300000084 +:100000006F00C00613000000130000001300000082 :100010001300000013000000130000001300000094 :10002000F32E003093FE0E08638A0E00B72E0000F8 :10003000938E0E8073900E3073002030F32E1034A8 -:10004000938E4E0073901E3473002030130E1000F8 -:100050003705001093054006130650069306600608 -:100060002320D5002F26B51813071000631AE614B5 -:10007000032705006396E614130E200037050010D1 -:100080001305450093057006130680069306900637 -:100090002320D5002F26B518130710006312E6128F -:1000A00003270500639EE610130E3000370500108D -:1000B0001305450093057006130680069306900607 -:1000C0002F26B51813071000631CE60E0327050042 -:1000D0006398E60E130E40003705001013058500E7 -:1000E0009305A0061306B0069306C0062320D5008C -:1000F000AF2705102F26B5186394D70C6312060C92 -:1001000003270500639EE50A130E50003705001013 -:10011000130585009305D0061306E0069306F00646 -:100120002320D5002F26B518630C060803270500E9 -:100130006398E608130E700037050010130545019B -:1001400093058007130690079306A007930E0001FE -:100150002320D500AF2705102F26B5186392D706A8 -:100160006310060603270500639CE504938EFEFFDB -:100170001305450093853500130636009386360037 -:10018000E3980EFC130E90003705001013050510C0 -:100190009305B0071306C0079306D0072320D500A8 -:1001A000AF27051073000000AF27B5181307000034 -:1001B0006398E700032705006394E5006F000001E2 -:1001C000370110F0130141F22320C101370110F073 -:1001D000130101F2232001001300000013000000AE -:1001E00013000000130000001300000013000000C3 -:040000058000004C2B +:10004000938E4E0073901E3473002030B702002050 +:10005000371300009303000203AE0200B382620074 +:100060009383F3FFE39A03FE67800000130E1000F2 +:1000700037050010930540061306500693066006E8 +:100080002320D5002F26B518130710006318E61893 +:10009000032705006394E618130E200037050010AF +:1000A0001305450093057006130680069306900617 +:1000B0002320D5002F26B518130710006310E6166D +:1000C00003270500639CE614EFF05FF803270500A3 +:1000D0006396E614130E3000370500101305450033 +:1000E0009305700613068006930690062F26B51812 +:1000F000130710006314E612032705006390E6124D +:10010000EFF0DFF403270500639AE610130E4000BA +:1001100037050010130585009305A0061306B006E9 +:100120009306C0062320D500AF2705102F26B5184B +:100130006396D70E6314060E032705006390E50E41 +:10014000EFF0DFF003270500639AE50C130E500073 +:1001500037050010130585009305D0061306E00649 +:100160009306F0062320D5002F26B5186308060A4B +:10017000032705006394E60AEFF05FED032705000F +:10018000639EE608130E7000370500101305450145 +:1001900093058007130690079306A007930E0001AE +:1001A0002320D500AF2705102F26B5186398D70652 +:1001B00063160606032705006392E506938EFEFF8D +:1001C00013054500938535001306360093863600E7 +:1001D000E3980EFC130E9000370500101305051070 +:1001E0009305B0071306C0079306D0072320D50058 +:1001F000AF27051073000000AF27B51813070000E4 +:10020000639EE70003270500639AE500EFF01FE413 +:10021000032705006394E5006F000001370110F02B +:10022000130141F22320C101370110F0130101F243 +:100230002320010013000000130000001300000041 +:0C02400013000000130000001300000079 +:040000058000006C0B :00000001FF diff --git a/src/test/cpp/raw/lrsc/src/crt.S b/src/test/cpp/raw/lrsc/src/crt.S index 0cddcd3..a19663f 100644 --- a/src/test/cpp/raw/lrsc/src/crt.S +++ b/src/test/cpp/raw/lrsc/src/crt.S @@ -25,8 +25,19 @@ notExternalInterrupt: csrw mepc, x29 mret +flush: + li t0, 0x20000000 + li t1, 0x1000 + li t2, 32 +flushLoop: + lw t3, 0(t0) + add t0, t0, t1 + addi t2,t2,-1 + bnez t2, flushLoop + ret + _start: -//Test 1 SC on unreserved area should fail and not write memory +test1: //Test 1 SC on unreserved area should fail and not write memory li x28, 1 li a0, 0x10000000 li a1, 100 @@ -39,7 +50,7 @@ _start: lw a4, 0(a0) bne a3, a4, fail -//Test 2 SC on another unreserved area should fail and not write memory +test2: //Test 2 SC on another unreserved area should fail and not write memory li x28, 2 li a0, 0x10000004 li a1, 103 @@ -51,9 +62,12 @@ _start: bne a2, a4, fail lw a4, 0(a0) bne a3, a4, fail + call flush + lw a4, 0(a0) + bne a3, a4, fail -//Test 3 retrying SC on unreserved area should fail and not write memory +test3: //Test 3 retrying SC on unreserved area should fail and not write memory li x28, 3 li a0, 0x10000004 li a1, 103 @@ -64,9 +78,12 @@ _start: bne a2, a4, fail lw a4, 0(a0) bne a3, a4, fail + call flush + lw a4, 0(a0) + bne a3, a4, fail -//Test 4 SC on reserved area should pass and should be written write memory +test4: //Test 4 SC on reserved area should pass and should be written write memory li x28, 4 li a0, 0x10000008 li a1, 106 @@ -79,9 +96,12 @@ _start: bne a2, x0, fail lw a4, 0(a0) bne a1, a4, fail + call flush + lw a4, 0(a0) + bne a1, a4, fail -//Test 5 redo SC on reserved area should fail +test5: //Test 5 redo SC on reserved area should fail li x28, 5 li a0, 0x10000008 li a1, 109 @@ -92,6 +112,9 @@ _start: beq a2, x0, fail lw a4, 0(a0) bne a3, a4, fail + call flush + lw a4, 0(a0) + bne a3, a4, fail //Test 7 do a lot of allocation to clear the entries @@ -131,7 +154,7 @@ test7: bne a5, a4, fail*/ -//Test 9 SC should pass after a context switching +test9: //Test 9 SC should pass after a context switching li x28, 9 li a0, 0x10000100 li a1, 123 @@ -145,6 +168,9 @@ test7: bne a5, a4, fail lw a4, 0(a0) bne a1, a4, fail + call flush + lw a4, 0(a0) + bne a1, a4, fail diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 9394144..8b959e2 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -1409,7 +1409,7 @@ public: virtual void fillSimELements(); void dump(int i){ #ifdef TRACE - if(i == TRACE_START && i != 0) cout << "START TRACE" << endl; + if(i == TRACE_START && i != 0) cout << "**" << endl << "**" << endl << "**" << endl << "**" << endl << "**" << endl << "START TRACE" << endl; if(i >= TRACE_START) tfp->dump(i); #endif } @@ -1518,7 +1518,7 @@ public: currentTime = i; #ifdef FLOW_INFO - if(i % 2000000 == 0) cout << "PROGRESS TRACE_START=" << i << endl; + if(i % 2000000 == 0) cout << "**" << endl << "**" << endl << "**" << endl << "**" << endl << "**" << endl << "PROGRESS TRACE_START=" << i << endl; #endif @@ -2314,16 +2314,25 @@ public: #ifdef DBUS_CACHED //#include "VVexRiscv_DataCache.h" +#include + +struct DBusCachedTask{ + uint32_t data; + bool error; + bool last; + bool exclusive; +}; class DBusCached : public SimElement{ public: - uint32_t address; - bool error_next = false; - uint32_t pendingCount = 0; - bool wr; + queue rsps; + + bool reservationValid = false; + uint32_t reservationAddress; Workspace *ws; VVexRiscv* top; + DBusCached(Workspace* ws){ this->ws = ws; this->top = ws->top; @@ -2345,41 +2354,63 @@ public: VL_IN8(io_cpu_execute_args_invalidate,0,0); VL_IN8(io_cpu_execute_args_way,0,0); -// if(top->VexRiscv->dataCache_1->io_cpu_execute_isValid && !top->VexRiscv->dataCache_1->io_cpu_execute_isStuck -// && top->VexRiscv->dataCache_1->io_cpu_execute_args_wr){ -// if(top->VexRiscv->dataCache_1->io_cpu_execute_args_address == 0x80025978) -// cout << "WR 0x80025978 = " << hex << setw(8) << top->VexRiscv->dataCache_1->io_cpu_execute_args_data << endl; -// if(top->VexRiscv->dataCache_1->io_cpu_execute_args_address == 0x8002596c) -// cout << "WR 0x8002596c = " << hex << setw(8) << top->VexRiscv->dataCache_1->io_cpu_execute_args_data << endl; -// } if (top->dBus_cmd_valid && top->dBus_cmd_ready) { - if(pendingCount == 0){ - pendingCount = top->dBus_cmd_payload_length+1; - address = top->dBus_cmd_payload_address; - wr = top->dBus_cmd_payload_wr; - } - if(top->dBus_cmd_payload_wr){ - ws->dBusAccess(address,top->dBus_cmd_payload_wr,2,top->dBus_cmd_payload_mask,&top->dBus_cmd_payload_data,&error_next); - address += 4; - pendingCount--; - } + if(top->dBus_cmd_payload_wr){ + #ifndef SMP + bool error; + ws->dBusAccess(top->dBus_cmd_payload_address,1,2,top->dBus_cmd_payload_mask,&top->dBus_cmd_payload_data,&error); + #else + bool cancel = false; + DBusCachedTask rsp; + if(top->dBus_cmd_payload_exclusive){ + bool hit = reservationValid && reservationAddress == top->dBus_cmd_payload_address; + rsp.exclusive = hit; + cancel = !hit; + reservationValid = false; + } + if(!cancel) ws->dBusAccess(top->dBus_cmd_payload_address,1,2,top->dBus_cmd_payload_mask,&top->dBus_cmd_payload_data,&rsp.error); + rsp.last = true; + rsps.push(rsp); + #endif + } else { + for(int beat = 0;beat <= top->dBus_cmd_payload_length;beat++){ + DBusCachedTask rsp; + ws->dBusAccess(top->dBus_cmd_payload_address + beat * 4,0,2,0,&rsp.data,&rsp.error); + rsp.last = beat == top->dBus_cmd_payload_length; + #ifdef SMP + rsp.exclusive = true; + reservationValid = true; + reservationAddress = top->dBus_cmd_payload_address; + #endif + rsps.push(rsp); + } + } } } virtual void postCycle(){ - if(pendingCount != 0 && !wr && (!ws->dStall || VL_RANDOM_I(7) < 100)){ - ws->dBusAccess(address,0,2,0,&top->dBus_rsp_payload_data,&error_next); - top->dBus_rsp_payload_error = error_next; + + if(!rsps.empty() && (!ws->dStall || VL_RANDOM_I(7) < 100)){ + DBusCachedTask rsp = rsps.front(); + rsps.pop(); top->dBus_rsp_valid = 1; - address += 4; - pendingCount--; + top->dBus_rsp_payload_error = rsp.error; + top->dBus_rsp_payload_data = rsp.data; + top->dBus_rsp_payload_last = rsp.last; + #ifdef SMP + top->dBus_rsp_payload_exclusive = rsp.exclusive; + #endif } else{ top->dBus_rsp_valid = 0; top->dBus_rsp_payload_data = VL_RANDOM_I(32); top->dBus_rsp_payload_error = VL_RANDOM_I(1); + top->dBus_rsp_payload_last = VL_RANDOM_I(1); + #ifdef SMP + top->dBus_rsp_payload_exclusive = VL_RANDOM_I(1); + #endif } - top->dBus_cmd_ready = (ws->dStall ? VL_RANDOM_I(7) < 100 : 1) && (pendingCount == 0 || wr); + top->dBus_cmd_ready = (ws->dStall ? VL_RANDOM_I(7) < 100 : 1); } }; #endif diff --git a/src/test/cpp/regression/makefile b/src/test/cpp/regression/makefile index 2278d06..fba824e 100644 --- a/src/test/cpp/regression/makefile +++ b/src/test/cpp/regression/makefile @@ -15,6 +15,7 @@ CSR_SKIP_TEST?=no EBREAK?=no FENCEI?=no MMU?=yes +SMP?=no SEED?=no LRSC?=no AMO?=no @@ -217,6 +218,10 @@ ifeq ($(MMU),yes) ADDCFLAGS += -CFLAGS -DMMU endif +ifeq ($(SMP),yes) + ADDCFLAGS += -CFLAGS -DSMP +endif + ifeq ($(MUL),yes) ADDCFLAGS += -CFLAGS -DMUL endif