diff --git a/src/main/scala/vexriscv/demo/SimpleBus.scala b/src/main/scala/vexriscv/demo/SimpleBus.scala
index 4239b67..e8a7404 100644
--- a/src/main/scala/vexriscv/demo/SimpleBus.scala
+++ b/src/main/scala/vexriscv/demo/SimpleBus.scala
@@ -228,8 +228,17 @@ case class SimpleBusInterconnect(){
   val slaves = mutable.LinkedHashMap[SimpleBus, SlaveModel]()
   val connections = ArrayBuffer[ConnectionModel]()
   var arbitrationPendingRspMaxDefault = 1
-  val arbitrationRspRouteQueueDefault = false
+  var arbitrationRspRouteQueueDefault = false
 
+  def perfConfig(): Unit ={
+    arbitrationPendingRspMaxDefault = 7
+    arbitrationRspRouteQueueDefault = true
+  }
+
+  def areaConfig(): Unit ={
+    arbitrationPendingRspMaxDefault = 1
+    arbitrationRspRouteQueueDefault = false
+  }
 
   def setConnector(bus : SimpleBus)( connector : (SimpleBus,SimpleBus) => Unit): Unit = (masters.get(bus), slaves.get(bus)) match {
     case (Some(m), _) =>    m.connector = connector
diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp
index 95e2511..ab9fab6 100644
--- a/src/test/cpp/regression/main.cpp
+++ b/src/test/cpp/regression/main.cpp
@@ -685,6 +685,7 @@ public:
     		ws->iBusAccessPatch(address,data,&error);
         }
         virtual bool dRead(int32_t address, int32_t size, uint32_t *data){
+            if(address & (size-1) != 0) cout << "Ref did a unaligned read" << endl;
     		if((address & 0xF0000000) == 0xF0000000){
 				MemRead t = periphRead.front();
 				if(t.address != address || t.size != size){
@@ -697,6 +698,7 @@ public:
     		}
         }
         virtual void dWrite(int32_t address, int32_t size, uint32_t data){
+            if(address & (size-1) != 0) cout << "Ref did a unaligned write" << endl;
     		if((address & 0xF0000000) == 0xF0000000){
 				MemWrite w;
 				w.address = address;
@@ -1023,7 +1025,7 @@ public:
 				#endif
                 if(top->VexRiscv->writeBack_arbitration_isFiring){
                    	if(riscvRefEnable && top->VexRiscv->writeBack_PC != riscvRef.pc){
-						cout << "pc missmatch" << endl;
+						cout << " pc missmatch " << top->VexRiscv->writeBack_PC << " should be " << riscvRef.pc << endl;
 						fail();
 					}
 
diff --git a/src/test/python/gcloud/run.sh b/src/test/python/gcloud/run.sh
index cd16afb..02c17f9 100644
--- a/src/test/python/gcloud/run.sh
+++ b/src/test/python/gcloud/run.sh
@@ -10,8 +10,8 @@ cd VexRiscv
 sudo git init
 sudo git add *
 sudo git commit -m miaou
-export VEXRISCV_REGRESSION_CONFIG_COUNT=64
-export VEXRISCV_REGRESSION_FREERTOS_COUNT=yes
+export VEXRISCV_REGRESSION_CONFIG_COUNT=128
+export VEXRISCV_REGRESSION_FREERTOS_COUNT=30
 sbt test
 cd ..
 
diff --git a/src/test/scala/vexriscv/TestIndividualFeatures.scala b/src/test/scala/vexriscv/TestIndividualFeatures.scala
index 0c0dd7a..10f25c9 100644
--- a/src/test/scala/vexriscv/TestIndividualFeatures.scala
+++ b/src/test/scala/vexriscv/TestIndividualFeatures.scala
@@ -523,8 +523,8 @@ class TestIndividualFeatures extends FunSuite {
 
 
 //  val testId = Some(mutable.HashSet[Int](0,28,45,93))
-//  val testId = Some(mutable.HashSet[Int](9))
-//  val seed = -8173808854505304814l
+//  val testId = Some(mutable.HashSet[Int](5))
+//  val seed = -2089952013329208578l