From 3060296b94f9ed60d4252fc712dcdb92eb054fc5 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 10 Nov 2017 11:33:04 +0100 Subject: [PATCH] unsetRegIfNoAssignement -> allowUnsetRegToAvoidLatch --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 57c4470..b9745ea 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -260,10 +260,10 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio //Define CSR registers val misa = new Area{ - val base = Reg(UInt(2 bits)) init(U"01") unsetRegIfNoAssignement - val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit) unsetRegIfNoAssignement + val base = Reg(UInt(2 bits)) init(U"01") allowUnsetRegToAvoidLatch + val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit) allowUnsetRegToAvoidLatch } - val mtvec = RegInit(U(mtvecInit,xlen bits)) unsetRegIfNoAssignement + val mtvec = RegInit(U(mtvecInit,xlen bits)) allowUnsetRegToAvoidLatch val mepc = Reg(UInt(xlen bits)) val mstatus = new Area{ val MIE, MPIE = RegInit(False) @@ -337,7 +337,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio val exceptionPortCtrl = if(exceptionPortsInfos.nonEmpty) new Area{ val firstStageIndexWithExceptionPort = exceptionPortsInfos.map(i => indexOf(i.stage)).min val exceptionValids = Vec(Bool,stages.length) - val exceptionValidsRegs = Vec(Reg(Bool) init(False), stages.length).unsetRegIfNoAssignement + val exceptionValidsRegs = Vec(Reg(Bool) init(False), stages.length).allowUnsetRegToAvoidLatch val exceptionContext = Reg(ExceptionCause()) val pipelineHasException = exceptionValids.orR //TODO FMAX maybe could be partialy pipelined