Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Improved the paragraph about available configurations.

This commit is contained in:
PythonLinks 2024-03-05 09:57:41 +01:00 committed by GitHub
parent fe5e6dd95b
commit 30871d3381
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 1 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
README.md
View File

@ -193,9 +193,7 @@ sudo make install
``` ```
## CPU generation ## CPU generation
You can find two example CPU instances in: We now have twenty-two CPU configurations [in this directory](./src/main/scala/vexriscv/demo). Look at the files called Gen*.scala. Here is the [full configuration](./src/main/scala/vexriscv/demo/GenFull.scala), and the [smallest configuration](./src/main/scala/vexriscv/demo/GenSmallest.scala).
- `src/main/scala/vexriscv/demo/GenFull.scala`
- `src/main/scala/vexriscv/demo/GenSmallest.scala`
To generate the corresponding RTL as a `VexRiscv.v` file, run the following commands in the root directory of this repository: To generate the corresponding RTL as a `VexRiscv.v` file, run the following commands in the root directory of this repository: