diff --git a/README.md b/README.md index 5e3c51a..c4196b1 100644 --- a/README.md +++ b/README.md @@ -681,18 +681,17 @@ case class IBusSimpleCmd() extends Bundle{ } case class IBusSimpleRsp() extends Bundle with IMasterSlave{ - val ready = Bool val error = Bool val inst = Bits(32 bits) override def asMaster(): Unit = { - out(ready,error,inst) + out(error,inst) } } case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMasterSlave{ var cmd = Stream(IBusSimpleCmd()) - var rsp = IBusSimpleRsp() + var rsp = Flow(IBusSimpleRsp()) override def asMaster(): Unit = { master(cmd) @@ -701,7 +700,8 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste } ``` -There is at least one cycle latency between que cmd and the rsp. the rsp.ready flag should be false after a cmd until the rsp is present. +**Important** : There should be at least one cycle latency between que cmd and the rsp. The IBus.cmd can remove request when a CPU jump occure or when the CPU is halted by someting in the pipeline. As many arbitration aren't made for this behaviour, it is important to add a buffer to the iBus.cmd to avoid this. Ex : iBus.cmd.s2mPipe, which add a zero latency buffer and cut the iBus.cmd.ready path. +You can also do iBus.cmd.s2mPipe.m2sPipe, which will cut all combinatorial path of the bus but then as a latency of 1 cycle. which mean you should probably set the busLatencyMin to 2. Note that bridges are implemented to convert this interface into AXI4 and Avalon diff --git a/build.sbt b/build.sbt index 901fc5e..499e838 100644 --- a/build.sbt +++ b/build.sbt @@ -2,15 +2,15 @@ name := "VexRiscv" organization := "com.github.spinalhdl" -version := "1.0" +version := "1.0.0" scalaVersion := "2.11.6" EclipseKeys.withSource := true libraryDependencies ++= Seq( - "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.1.6", - "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.1.6", + "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.2.0", + "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.2.0", "org.scalatest" % "scalatest_2.11" % "2.2.1", "org.yaml" % "snakeyaml" % "1.8" ) @@ -19,4 +19,4 @@ libraryDependencies ++= Seq( addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2") scalacOptions += "-P:continuations:enable" -fork := true \ No newline at end of file +fork := true diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala index 53d6aa8..afd29bb 100644 --- a/src/main/scala/vexriscv/VexRiscv.scala +++ b/src/main/scala/vexriscv/VexRiscv.scala @@ -6,7 +6,7 @@ import spinal.core._ import scala.collection.mutable.ArrayBuffer object VexRiscvConfig{ - def apply(plugins : Seq[Plugin[VexRiscv]]) : VexRiscvConfig = { + def apply(plugins : Seq[Plugin[VexRiscv]] = ArrayBuffer()) : VexRiscvConfig = { val config = VexRiscvConfig() config.plugins ++= plugins config diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala index e0729c9..f908586 100644 --- a/src/main/scala/vexriscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -101,17 +101,17 @@ object VexRiscvSynthesisBench { } -// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) -val rtls = List(smallestNoCsr) + val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) +//val rtls = List(smallestNoCsr) // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) // val rtls = List(smallAndProductive, full) - val targets = /*XilinxStdTargets( + val targets = XilinxStdTargets( vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" ) ++ AlteraStdTargets( quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin" - ) ++ */IcestormStdTargets() + ) ++ IcestormStdTargets() // val targets = IcestormStdTargets() Bench(rtls, targets, "/eda/tmp/") diff --git a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala index ac72b40..35cad08 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala @@ -24,16 +24,16 @@ object VexRiscvCachedWishboneForSim{ //CPU configuration val cpuConfig = VexRiscvConfig( plugins = List( - new PcManagerSimplePlugin(0x00000000l, false), // new IBusSimplePlugin( -// interfaceKeepData = false, -// catchAccessFault = false +// resetVector = 0x80000000l, +// prediction = STATIC // ), // new DBusSimplePlugin( // catchAddressMisaligned = false, // catchAccessFault = false // ), new IBusCachedPlugin( + resetVector = 0x80000000l, prediction = STATIC, config = InstructionCacheConfig( cacheSize = 4096, @@ -79,7 +79,7 @@ object VexRiscvCachedWishboneForSim{ ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, - zeroBoot = false + zeroBoot = true ), new IntAluPlugin, new SrcPlugin( @@ -117,36 +117,22 @@ object VexRiscvCachedWishboneForSim{ //cpu.setDefinitionName("VexRiscvAvalon") cpu.rework { for (plugin <- cpuConfig.plugins) plugin match { -// case plugin: IBusSimplePlugin => { -// plugin.iBus.asDirectionLess() //Unset IO properties of iBus -// iBus = master(plugin.iBus.toAvalon()) -// .setName("iBusAvalon") -// .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) -// } - case plugin: IBusCachedPlugin => { + case plugin: IBusSimplePlugin => { plugin.iBus.asDirectionLess() //Unset IO properties of iBus master(plugin.iBus.toWishbone()).setName("iBusWishbone") } -// case plugin: DBusSimplePlugin => { -// plugin.dBus.asDirectionLess() -// master(plugin.dBus.toAvalon()) -// .setName("dBusAvalon") -// .addTag(ClockDomainTag(ClockDomain.current)) -// } + case plugin: IBusCachedPlugin => { + plugin.iBus.asDirectionLess() + master(plugin.iBus.toWishbone()).setName("iBusWishbone") + } + case plugin: DBusSimplePlugin => { + plugin.dBus.asDirectionLess() + master(plugin.dBus.toWishbone()).setName("dBusWishbone") + } case plugin: DBusCachedPlugin => { plugin.dBus.asDirectionLess() master(plugin.dBus.toWishbone()).setName("dBusWishbone") } -// case plugin: DebugPlugin => { -// plugin.io.bus.asDirectionLess() -// slave(plugin.io.bus.fromAvalon()) -// .setName("debugBusAvalon") -// .addTag(ClockDomainTag(plugin.debugClockDomain)) -// .parent = null //Avoid the io bundle to be interpreted as a QSys conduit -// plugin.io.resetOut -// .addTag(ResetEmitterTag(plugin.debugClockDomain)) -// .parent = null //Avoid the io bundle to be interpreted as a QSys conduit -// } case _ => } } diff --git a/src/main/scala/vexriscv/plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala index 2c38653..eff2f09 100644 --- a/src/main/scala/vexriscv/plugin/BranchPlugin.scala +++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala @@ -49,7 +49,7 @@ trait PredictionInterface{ } class BranchPlugin(earlyBranch : Boolean, - catchAddressMisaligned : Boolean) extends Plugin[VexRiscv] with PredictionInterface{ + catchAddressMisaligned : Boolean = false) extends Plugin[VexRiscv] with PredictionInterface{ lazy val branchStage = if(earlyBranch) pipeline.execute else pipeline.memory @@ -218,7 +218,7 @@ class BranchPlugin(earlyBranch : Boolean, ) ) - insert(BRANCH_DO) := input(PREDICTION_HAD_BRANCHED) =/= insert(BRANCH_COND_RESULT) + insert(BRANCH_DO) := input(PREDICTION_HAD_BRANCHED) =/= input(BRANCH_COND_RESULT) //Calculation of the branch target / correction val imm = IMM(input(INSTRUCTION)) diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index 060dcca..102bbe9 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -4,7 +4,9 @@ import vexriscv._ import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba4.axi._ -import spinal.lib.bus.avalon.{AvalonMMConfig, AvalonMM} +import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig} +import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig} +import vexriscv.ip.DataCacheMemCmd case class DBusSimpleCmd() extends Bundle{ @@ -45,6 +47,21 @@ object DBusSimpleBus{ useResponse = true, maximumPendingReadTransactions = 1 ) + + def getWishboneConfig() = WishboneConfig( + addressWidth = 30, + dataWidth = 32, + selWidth = 4, + useSTALL = false, + useLOCK = false, + useERR = true, + useRTY = false, + tgaWidth = 0, + tgcWidth = 0, + tgdWidth = 0, + useBTE = true, + useCTI = true + ) } case class DBusSimpleBus() extends Bundle with IMasterSlave{ @@ -133,10 +150,39 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ mm } + + def toWishbone(): Wishbone = { + val wishboneConfig = DBusSimpleBus.getWishboneConfig() + val bus = Wishbone(wishboneConfig) + val cmdStage = cmd.halfPipe() + + bus.ADR := cmdStage.address >> 2 + bus.CTI :=B"000" + bus.BTE := "00" + bus.SEL := (cmdStage.size.mux ( + U(0) -> B"0001", + U(1) -> B"0011", + default -> B"1111" + ) << cmdStage.address(1 downto 0)).resized + when(!cmdStage.wr) { + bus.SEL := "1111" + } + bus.WE := cmdStage.wr + bus.DAT_MOSI := cmdStage.data + + cmdStage.ready := cmdStage.valid && bus.ACK + bus.CYC := cmdStage.valid + bus.STB := cmdStage.valid + + rsp.ready := cmdStage.valid && !bus.WE && bus.ACK + rsp.data := bus.DAT_MISO + rsp.error := False //TODO + bus + } } -class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Boolean, earlyInjection : Boolean = false) extends Plugin[VexRiscv]{ +class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, catchAccessFault : Boolean = false, earlyInjection : Boolean = false) extends Plugin[VexRiscv]{ var dBus : DBusSimpleBus = null diff --git a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala index 877c6a0..ad33efc 100644 --- a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala @@ -44,7 +44,7 @@ case class Masked(value : BigInt,care : BigInt){ def toString(bitCount : Int) = (0 until bitCount).map(i => if(care.testBit(i)) (if(value.testBit(i)) "1" else "0") else "-").reverseIterator.reduce(_+_) } -class DecoderSimplePlugin(catchIllegalInstruction : Boolean, forceLegalInstructionComputation : Boolean = false) extends Plugin[VexRiscv] with DecoderService { +class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false, forceLegalInstructionComputation : Boolean = false) extends Plugin[VexRiscv] with DecoderService { override def add(encoding: Seq[(MaskedLiteral, Seq[(Stageable[_ <: BaseType], Any)])]): Unit = encoding.foreach(e => this.add(e._1,e._2)) override def add(key: MaskedLiteral, values: Seq[(Stageable[_ <: BaseType], Any)]): Unit = { val instructionModel = encodings.getOrElseUpdate(key,ArrayBuffer[(Stageable[_ <: BaseType], BaseType)]()) diff --git a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala index 88f492d..cb013b8 100644 --- a/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala @@ -5,10 +5,10 @@ import spinal.core._ import spinal.lib._ -class HazardSimplePlugin(bypassExecute : Boolean, - bypassMemory: Boolean, - bypassWriteBack: Boolean, - bypassWriteBackBuffer : Boolean, +class HazardSimplePlugin(bypassExecute : Boolean = false, + bypassMemory: Boolean = false, + bypassWriteBack: Boolean = false, + bypassWriteBackBuffer : Boolean = false, pessimisticUseSrc : Boolean = false, pessimisticWriteRegFile : Boolean = false, pessimisticAddressMatch : Boolean = false) extends Plugin[VexRiscv] { diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index 57dbdff..523a2ef 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -5,6 +5,7 @@ import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba4.axi._ import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig} +import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig} @@ -43,6 +44,21 @@ object IBusSimpleBus{ useResponse = true, maximumPendingReadTransactions = 8 ) + + def getWishboneConfig() = WishboneConfig( + addressWidth = 30, + dataWidth = 32, + selWidth = 4, + useSTALL = false, + useLOCK = false, + useERR = true, + useRTY = false, + tgaWidth = 0, + tgcWidth = 0, + tgdWidth = 0, + useBTE = true, + useCTI = true + ) } @@ -96,6 +112,29 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste mm } + + def toWishbone(): Wishbone = { + val wishboneConfig = IBusSimpleBus.getWishboneConfig() + val bus = Wishbone(wishboneConfig) + val cmdPipe = cmd.stage() + + bus.ADR := (cmdPipe.pc >> 2) + bus.CTI := B"000" + bus.BTE := "00" + bus.SEL := "1111" + bus.WE := False + bus.DAT_MOSI.assignDontCare() + bus.CYC := cmdPipe.valid + bus.STB := cmdPipe.valid + + + cmdPipe.ready := cmdPipe.valid && bus.ACK + rsp.valid := bus.CYC && bus.ACK + rsp.inst := bus.DAT_MISO + rsp.error := False //TODO + bus + } + } diff --git a/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala b/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala index 1d74c2b..4c72131 100644 --- a/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala +++ b/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala @@ -64,7 +64,7 @@ class MemoryTranslatorPlugin(tlbSize : Int, val shared = new Area { val cache = Mem(CacheLine(), tlbSize) var free = True - val readAddr = cache.addressType.assignDontCare() + val readAddr = cache.addressType().assignDontCare() val readData = RegNext(cache.readSync(readAddr)) } diff --git a/src/main/scala/vexriscv/plugin/Misc.scala b/src/main/scala/vexriscv/plugin/Misc.scala index 5a81bbc..b8ddd8e 100644 --- a/src/main/scala/vexriscv/plugin/Misc.scala +++ b/src/main/scala/vexriscv/plugin/Misc.scala @@ -126,7 +126,7 @@ object StreamVexPimper{ val ret = cloneOf(pimped) val rValid = RegInit(False) - val rData = Reg(pimped.dataType) + val rData = Reg(pimped.payloadType) if(!discardInput) rValid.clearWhen(flush) pimped.ready := (Bool(collapsBubble) && !ret.valid) || ret.ready @@ -148,7 +148,7 @@ object StreamVexPimper{ val ret = cloneOf(pimped) val rValid = RegInit(False) - val rBits = Reg(pimped.dataType) + val rBits = Reg(pimped.payloadType) ret.valid := pimped.valid || rValid pimped.ready := !rValid diff --git a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala index 356e10f..71a519e 100644 --- a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala +++ b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala @@ -4,7 +4,7 @@ import spinal.core._ import spinal.lib._ import vexriscv.{VexRiscv, _} -class MulDivIterativePlugin(genMul : Boolean, genDiv : Boolean, mulUnrollFactor : Int, divUnrollFactor : Int) extends Plugin[VexRiscv]{ +class MulDivIterativePlugin(genMul : Boolean = true, genDiv : Boolean = true, mulUnrollFactor : Int = 1, divUnrollFactor : Int = 1) extends Plugin[VexRiscv]{ object IS_MUL extends Stageable(Bool) object IS_DIV extends Stageable(Bool) object IS_REM extends Stageable(Bool) diff --git a/src/main/scala/vexriscv/plugin/SrcPlugin.scala b/src/main/scala/vexriscv/plugin/SrcPlugin.scala index 8b82c7f..da9b151 100644 --- a/src/main/scala/vexriscv/plugin/SrcPlugin.scala +++ b/src/main/scala/vexriscv/plugin/SrcPlugin.scala @@ -4,7 +4,7 @@ import vexriscv.{RVC_GEN, Riscv, VexRiscv} import spinal.core._ -class SrcPlugin(separatedAddSub : Boolean, executeInsertion : Boolean = false) extends Plugin[VexRiscv]{ +class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = false) extends Plugin[VexRiscv]{ override def build(pipeline: VexRiscv): Unit = { import pipeline._ import pipeline.config._ diff --git a/src/test/scala/vexriscv/Swing.scala b/src/main/scala/vexriscv/test/Swing.scala similarity index 98% rename from src/test/scala/vexriscv/Swing.scala rename to src/main/scala/vexriscv/test/Swing.scala index 261a79c..b3a1637 100644 --- a/src/test/scala/vexriscv/Swing.scala +++ b/src/main/scala/vexriscv/test/Swing.scala @@ -1,7 +1,7 @@ -package vexriscv +package vexriscv.test -import java.awt.{Color, Dimension, Graphics} import java.awt.event.{MouseEvent, MouseListener} +import java.awt.{Color, Dimension, Graphics} import javax.swing.JPanel abstract class JLedArray(ledCount : Int,ledDiameter : Int = 20, blackThickness : Int = 2) extends JPanel{ diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 3c7f677..40478de 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -624,6 +624,8 @@ public: bool error; }; + uint32_t periphWriteTimer = 0; + queue periphWritesGolden; queue periphWrites; queue periphRead; Workspace *ws; @@ -663,11 +665,11 @@ public: } virtual void dWrite(int32_t address, int32_t size, uint32_t data){ if((address & 0xF0000000) == 0xF0000000){ - MemWrite t = periphWrites.front(); - if(t.address != address || t.size != size || t.data != data){ - fail(); - } - periphWrites.pop(); + MemWrite w; + w.address = address; + w.size = size; + w.data = data; + periphWritesGolden.push(w); }else { mem.write(address, size, (uint8_t*)&data); } @@ -677,6 +679,23 @@ public: void step() { rfWriteValid = false; RiscvGolden::step(); + + switch(periphWrites.empty() + uint32_t(periphWritesGolden.empty())*2){ + case 3: periphWriteTimer = 0; break; + case 1: case 2: if(periphWriteTimer++ == 20){ cout << "periphWrite timout" << endl; fail();} break; + case 0: + MemWrite t = periphWrites.front(); + MemWrite t2 = periphWritesGolden.front(); + if(t.address != t2.address || t.size != t2.size || t.data != t2.data){ + cout << "periphWrite missmatch" << endl; + fail(); + } + periphWrites.pop(); + periphWritesGolden.pop(); + break; + } + + } }; @@ -903,7 +922,7 @@ public: if(bootPc != -1) top->VexRiscv->core->prefetch_pc = bootPc; #else if(bootPc != -1) { - #ifdef IBUS_SIMPLE + #if defined(IBUS_SIMPLE) || defined(IBUS_SIMPLE_WISHBONE) top->VexRiscv->IBusSimplePlugin_fetchPc_pcReg = bootPc; #ifdef COMPRESSED top->VexRiscv->IBusSimplePlugin_decodePc_pcReg = bootPc; @@ -1261,10 +1280,9 @@ public: #endif -#ifdef IBUS_CACHED_WISHBONE +#if defined(IBUS_CACHED_WISHBONE) || defined(IBUS_SIMPLE_WISHBONE) #include - class IBusCachedWishbone : public SimElement{ public: @@ -1282,21 +1300,24 @@ public: } virtual void preCycle(){ - top->iBusWishbone_DAT_MISO = VL_RANDOM_I(32); - if (top->iBusWishbone_CYC && top->iBusWishbone_STB && top->iBusWishbone_ACK) { - if(top->iBusWishbone_WE){ - } else { - bool error; - ws->iBusAccess(top->iBusWishbone_ADR << 2,&top->iBusWishbone_DAT_MISO,&error); - top->iBusWishbone_ERR = error; - } - } } virtual void postCycle(){ + if(ws->iStall) top->iBusWishbone_ACK = VL_RANDOM_I(7) < 100; + + top->iBusWishbone_DAT_MISO = VL_RANDOM_I(32); + if (top->iBusWishbone_CYC && top->iBusWishbone_STB && top->iBusWishbone_ACK) { + if(top->iBusWishbone_WE){ + + } else { + bool error; + ws->iBusAccess(top->iBusWishbone_ADR << 2,&top->iBusWishbone_DAT_MISO,&error); + top->iBusWishbone_ERR = error; + } + } } }; #endif @@ -1398,7 +1419,7 @@ public: }; #endif -#ifdef DBUS_CACHED_WISHBONE +#if defined(DBUS_CACHED_WISHBONE) || defined(DBUS_SIMPLE_WISHBONE) #include @@ -1419,22 +1440,23 @@ public: } virtual void preCycle(){ - top->dBusWishbone_DAT_MISO = VL_RANDOM_I(32); - if (top->dBusWishbone_CYC && top->dBusWishbone_STB && top->dBusWishbone_ACK) { - if(top->dBusWishbone_WE){ - bool dummy; - ws->dBusAccess(top->dBusWishbone_ADR << 2 ,1,2,top->dBusWishbone_SEL,&top->dBusWishbone_DAT_MOSI,&dummy); - } else { - bool error; - ws->dBusAccess(top->dBusWishbone_ADR << 2,0,2,0xF,&top->dBusWishbone_DAT_MISO,&error); - top->dBusWishbone_ERR = error; - } - } + } virtual void postCycle(){ if(ws->iStall) top->dBusWishbone_ACK = VL_RANDOM_I(7) < 100; + top->dBusWishbone_DAT_MISO = VL_RANDOM_I(32); + if (top->dBusWishbone_CYC && top->dBusWishbone_STB && top->dBusWishbone_ACK) { + if(top->dBusWishbone_WE){ + bool dummy; + ws->dBusAccess(top->dBusWishbone_ADR << 2 ,1,2,top->dBusWishbone_SEL,&top->dBusWishbone_DAT_MOSI,&dummy); + } else { + bool error; + ws->dBusAccess(top->dBusWishbone_ADR << 2,0,2,0xF,&top->dBusWishbone_DAT_MISO,&error); + top->dBusWishbone_ERR = error; + } + } } }; #endif @@ -1871,7 +1893,7 @@ void Workspace::fillSimELements(){ #ifdef IBUS_CACHED_AVALON simElements.push_back(new IBusCachedAvalon(this)); #endif - #ifdef IBUS_CACHED_WISHBONE + #if defined(IBUS_CACHED_WISHBONE) || defined(IBUS_SIMPLE_WISHBONE) simElements.push_back(new IBusCachedWishbone(this)); #endif #ifdef DBUS_SIMPLE @@ -1886,7 +1908,7 @@ void Workspace::fillSimELements(){ #ifdef DBUS_CACHED_AVALON simElements.push_back(new DBusCachedAvalon(this)); #endif - #ifdef DBUS_CACHED_WISHBONE + #if defined(DBUS_CACHED_WISHBONE) || defined(DBUS_SIMPLE_WISHBONE) simElements.push_back(new DBusCachedWishbone(this)); #endif #ifdef DEBUG_PLUGIN_STD diff --git a/src/test/scala/vexriscv/MuraxSim.scala b/src/test/scala/vexriscv/MuraxSim.scala index bc80030..46131cd 100644 --- a/src/test/scala/vexriscv/MuraxSim.scala +++ b/src/test/scala/vexriscv/MuraxSim.scala @@ -11,6 +11,7 @@ import javax.swing._ import spinal.lib.com.jtag.sim.JtagTcp import spinal.lib.com.uart.sim.{UartDecoder, UartEncoder} +import vexriscv.test.{JLedArray, JSwitchArray} import scala.collection.mutable @@ -21,7 +22,7 @@ object MuraxSim { // def config = MuraxConfig.default.copy(onChipRamSize = 256 kB) def config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex") - SimConfig.allOptimisation.compile(new Murax(config)).doSimUntilVoid{dut => + SimConfig.allOptimisation.withWave.compile(new Murax(config)).doSimUntilVoid{dut => val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong val jtagClkPeriod = mainClkPeriod*4 val uartBaudRate = 115200 diff --git a/src/test/scala/vexriscv/experimental/config.scala b/src/test/scala/vexriscv/experimental/config.scala new file mode 100644 index 0000000..b44e662 --- /dev/null +++ b/src/test/scala/vexriscv/experimental/config.scala @@ -0,0 +1,36 @@ +package vexriscv.experimental + +import spinal.core.SpinalVerilog +import vexriscv.ip.InstructionCacheConfig +import vexriscv.{VexRiscv, VexRiscvConfig, plugin} +import vexriscv.plugin._ + +import scala.collection.mutable.ArrayBuffer + +object Presentation extends App{ + + val config = VexRiscvConfig() + + config.plugins ++= List( + new IBusSimplePlugin(resetVector = 0x80000000l), + new DBusSimplePlugin, + new CsrPlugin(CsrPluginConfig.smallest), + new DecoderSimplePlugin, + new RegFilePlugin(regFileReadyKind = plugin.SYNC), + new IntAluPlugin, + new SrcPlugin, + new MulDivIterativePlugin( + mulUnrollFactor = 4, + divUnrollFactor = 1 + ), + new FullBarrelShifterPlugin, + new HazardSimplePlugin, + new BranchPlugin( + earlyBranch = false + ), + new YamlPlugin("cpu0.yaml") + ) + + new VexRiscv(config) +} +