diff --git a/README.md b/README.md index 0a901cb..1a3b908 100644 --- a/README.md +++ b/README.md @@ -282,9 +282,9 @@ You can find some FPGA projects which instantiate the Briey SoC here (DE1-SoC, D Here are some measurements of Briey SoC timings and area : ``` - Artix 7 -> 239 Mhz 3227 LUT 3410 FF - Cyclone V -> 125 Mhz 2,207 ALMs - Cyclone IV -> 112 Mhz 4,594 LUT 3,620 + Artix 7 -> 233 Mhz 3035 LUT 3289 FF + Cyclone V -> 114 Mhz 2,073 ALMs + Cyclone IV -> 101 Mhz 4,279 LUT 3,167 FF ``` ## Murax SoC diff --git a/src/main/scala/vexriscv/demo/Linux.scala b/src/main/scala/vexriscv/demo/Linux.scala index d075725..85fc2ed 100644 --- a/src/main/scala/vexriscv/demo/Linux.scala +++ b/src/main/scala/vexriscv/demo/Linux.scala @@ -50,7 +50,7 @@ make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRE Run linux with QEMU (Require the machime mode emulator compiled in QEMU mode) export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal -qemu-system-riscv32 -nographic -machine virt -m 1536M -device loader,file=src/main/c/emulator/build/emulator.bin,addr=0x80000000,cpu-num=0 -device loader,file=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb,addr=0xC3000000 -device loader,file=$BUILDROOT/output/images/vmlinux.bin,addr=0xC0000000 -device loader,file=$BUILDROOT/output/images/rootfs.cpio,addr=0xc2000000 +qemu-system-riscv32 -nographic -machine virt -m 1536M -device loader,file=src/main/c/emulator/build/emulator.bin,addr=0x80000000,cpu-num=0 -device loader,file=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb,addr=0xC3000000 -device loader,file=$BUILDROOT/output/images/Image,addr=0xC0000000 -device loader,file=$BUILDROOT/output/images/rootfs.cpio,addr=0xc2000000 Buildroot => @@ -92,7 +92,7 @@ export DATA=/home/miaou/Downloads/Binaries-master cd src/test/cpp/regression rm VexRiscv.v cp $DATA/VexRiscv.v ../../../.. -make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=yess LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=$DATA/emulator.bin VMLINUX=$DATA/vmlinux.bin DTB=$DATA/rv32.dtb RAMDISK=$DATA/rootfs.cpio TRACE=no FLOW_INFO=no +make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=no LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=$DATA/emulator.bin VMLINUX=$DATA/vmlinux.bin DTB=$DATA/rv32.dtb RAMDISK=$DATA/rootfs.cpio TRACE=no FLOW_INFO=no qemu-system-riscv32 -nographic -machine virt -m 1536M -device loader,file=$DATA/emulator.bin,addr=0x80000000,cpu-num=0 -device loader,file=$DATA/rv32.dtb,addr=0xC3000000 -device loader,file=$DATA/vmlinux.bin,addr=0xC0000000 -device loader,file=$DATA/rootfs.cpio,addr=0xc2000000 @@ -106,19 +106,23 @@ program ../../../main/c/emulator/build/emulator.bin 0x80000000 verify soc.loadBin(RAMDISK, 0xC2000000); export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal -make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=yes LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes +make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=no LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=/home/miaou/pro/riscv/buildrootSpinal/output/images/Image DTB=/home/miaou/pro/riscv/buildrootSpinal/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=/home/miaou/pro/riscv/buildrootSpinal/output/images/rootfs.cpio TRACE=no FLOW_INFO=no -make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=yes LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes DEBUG_PLUGIN_EXTERNAL=yes +make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=no LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes DEBUG_PLUGIN_EXTERNAL=yes rm -rf cpio mkdir cpio cd cpio -ls | cpio -ov > ../rootfs.cpio cpio -idv < ../rootfs.cpio +cd .. + + +ls | cpio -ov > ../rootfs.cpio + */ @@ -147,12 +151,12 @@ object LinuxGen { new IBusCachedPlugin( resetVector = 0x80000000l, compressedGen = false, - prediction = NONE, + prediction = DYNAMIC_TARGET, injectorStage = false, config = InstructionCacheConfig( - cacheSize = 4096*1, + cacheSize = 4096*4, bytePerLine = 32, - wayCount = 1, + wayCount = 4, addressWidth = 32, cpuDataWidth = 32, memDataWidth = 32, @@ -182,9 +186,9 @@ object LinuxGen { dBusCmdSlavePipe = true, dBusRspSlavePipe = true, config = new DataCacheConfig( - cacheSize = 4096*1, + cacheSize = 4096*4, bytePerLine = 32, - wayCount = 1, + wayCount = 4, addressWidth = 32, cpuDataWidth = 32, memDataWidth = 32, @@ -404,7 +408,7 @@ object LinuxSyntesisBench extends App{ SpinalConfig(inlineRom=true).generateVerilog(new VexRiscv(LinuxGen.configFull(litex = false, withMmu = true)).setDefinitionName(getRtlPath().split("\\.").head)) } - val rtls = List(/*withoutMmu, */withMmu) + val rtls = List(withoutMmu,withMmu) // val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache) // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) // val rtls = List(fullNoMmu) diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala index 29ee27e..7976ac0 100644 --- a/src/main/scala/vexriscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -135,13 +135,13 @@ object BrieySynthesisBench { val rtls = List(briey) val targets = XilinxStdTargets( - vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" + vivadoArtix7Path = "/media/miaou/HD/linux/Xilinx/Vivado/2018.3/bin" ) ++ AlteraStdTargets( - quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/", - quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/" + quartusCycloneIVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin", + quartusCycloneVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin" ) - Bench(rtls, targets, "/eda/tmp/") + Bench(rtls, targets, "/media/miaou/HD/linux/tmp") } } @@ -174,14 +174,13 @@ object MuraxSynthesisBench { val rtls = List(murax, muraxFast) val targets = IcestormStdTargets().take(1) ++ XilinxStdTargets( - vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" + vivadoArtix7Path = "/media/miaou/HD/linux/Xilinx/Vivado/2018.3/bin" ) ++ AlteraStdTargets( - quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/", - quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/" + quartusCycloneIVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin", + quartusCycloneVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin" ) - - Bench(rtls, targets, "/eda/tmp/") + Bench(rtls, targets, "/media/miaou/HD/linux/tmp") } } diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index c83e5d6..5b1a6fc 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -55,6 +55,7 @@ case class CsrPluginConfig( noCsrAlu : Boolean = false, wfiGenAsNop : Boolean = false, ebreakGen : Boolean = false, + userGen : Boolean = false, supervisorGen : Boolean = false, sscratchGen : Boolean = false, stvecAccess : CsrAccess = CsrAccess.NONE, @@ -70,7 +71,7 @@ case class CsrPluginConfig( deterministicInteruptionEntry : Boolean = false //Only used for simulatation purposes ){ assert(!ucycleAccess.canWrite) - + def privilegeGen = userGen || supervisorGen def noException = this.copy(ecallGen = false, ebreakGen = false, catchIllegalAccess = false) } @@ -101,6 +102,7 @@ object CsrPluginConfig{ noCsrAlu = false, wfiGenAsNop = false, ebreakGen = true, + userGen = true, supervisorGen = true, sscratchGen = true, stvecAccess = CsrAccess.READ_WRITE, @@ -140,6 +142,7 @@ object CsrPluginConfig{ noCsrAlu = false, wfiGenAsNop = false, ebreakGen = true, + userGen = true, supervisorGen = true, sscratchGen = true, stvecAccess = CsrAccess.READ_WRITE, @@ -473,8 +476,9 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception val base = UInt(xlen-2 bits) } - val privilegeReg = RegInit(U"11") - privilege := privilegeReg + val privilegeReg = privilegeGen generate RegInit(U"11") + privilege := (if(privilegeGen) privilegeReg else U"11") + when(forceMachineWire) { privilege := 3 } val machineCsr = pipeline plug new Area{ @@ -798,7 +802,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception jumpInterface.payload := (if(!xtvecModeGen) xtvec.base @@ "00" else (xtvec.mode === 0 || hadException) ? (xtvec.base @@ "00") | ((xtvec.base + trapCause) @@ "00") ) beforeLastStage.arbitration.flushAll := True - privilegeReg := targetPrivilege + if(privilegeGen) privilegeReg := targetPrivilege switch(targetPrivilege){ if(supervisorGen) is(1) { @@ -841,15 +845,15 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception mstatus.MPP := U"00" mstatus.MIE := mstatus.MPIE mstatus.MPIE := True - privilegeReg := mstatus.MPP jumpInterface.payload := mepc + if(privilegeGen) privilegeReg := mstatus.MPP } if(supervisorGen) is(1){ sstatus.SPP := U"0" sstatus.SIE := sstatus.SPIE sstatus.SPIE := True - privilegeReg := U"0" @@ sstatus.SPP jumpInterface.payload := sepc + if(privilegeGen) privilegeReg := U"0" @@ sstatus.SPP } } } diff --git a/src/main/scala/vexriscv/plugin/SrcPlugin.scala b/src/main/scala/vexriscv/plugin/SrcPlugin.scala index 79bc763..9085ed1 100644 --- a/src/main/scala/vexriscv/plugin/SrcPlugin.scala +++ b/src/main/scala/vexriscv/plugin/SrcPlugin.scala @@ -64,7 +64,7 @@ class SrcPlugin(separatedAddSub : Boolean = false, executeInsertion : Boolean = import addSubStage._ // ADD, SUB - val addSub = (input(SRC1).asSInt + Mux(input(SRC_USE_SUB_LESS), ~input(SRC2), input(SRC2)).asSInt + Mux(input(SRC_USE_SUB_LESS), S(1), S(0))).asBits + val addSub = (input(SRC1).asSInt + Mux(input(SRC_USE_SUB_LESS), ~input(SRC2), input(SRC2)).asSInt + Mux(input(SRC_USE_SUB_LESS), S(1, 32 bits), S(0, 32 bits))).asBits when(input(SRC2_FORCE_ZERO)){ addSub := input(SRC1) }