From 33e820bdf994cf0b99abb0439b82e2c69496a9e4 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Wed, 8 Feb 2023 15:16:53 +0100
Subject: [PATCH] FPU now implement a less pessismitic dirty logic

---
 src/main/scala/vexriscv/ip/fpu/Interface.scala | 1 +
 src/main/scala/vexriscv/plugin/FpuPlugin.scala | 7 +++++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/vexriscv/ip/fpu/Interface.scala b/src/main/scala/vexriscv/ip/fpu/Interface.scala
index 9338c35..58cc017 100644
--- a/src/main/scala/vexriscv/ip/fpu/Interface.scala
+++ b/src/main/scala/vexriscv/ip/fpu/Interface.scala
@@ -144,6 +144,7 @@ case class FpuParameter( withDouble : Boolean,
 
 case class FpuFlags() extends Bundle{
   val NX,  UF,  OF,  DZ,  NV = Bool()
+  def any = List(NX,  UF,  OF,  DZ,  NV).orR
 }
 
 case class FpuCompletion() extends Bundle{
diff --git a/src/main/scala/vexriscv/plugin/FpuPlugin.scala b/src/main/scala/vexriscv/plugin/FpuPlugin.scala
index 6989753..8df6fa8 100644
--- a/src/main/scala/vexriscv/plugin/FpuPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/FpuPlugin.scala
@@ -216,8 +216,8 @@ class FpuPlugin(externalFpu : Boolean = false,
       val fs = Reg(Bits(2 bits)) init(1)
       val sd = fs === 3
 
-      when(stages.last.arbitration.isFiring && stages.last.input(FPU_ENABLE) && stages.last.input(FPU_OPCODE) =/= FpuOpcode.STORE){
-        fs := 3 //DIRTY
+      when(port.completion.fire && (port.completion.written || port.completion.flags.any)){
+        fs := 3
       }
       when(List(CSR.FRM, CSR.FCSR, CSR.FFLAGS).map(id => service.isWriting(id)).orR){
         fs := 3
@@ -298,6 +298,9 @@ class FpuPlugin(externalFpu : Boolean = false,
           when(!arbitration.isStuck && !arbitration.isRemoved){
             csr.flags.NV setWhen(port.rsp.NV)
             csr.flags.NX setWhen(port.rsp.NX)
+            when(port.rsp.NV || port.rsp.NX){
+              csr.fs := 3
+            }
           }
         }
         when(!port.rsp.valid){