From 342b06128f5a147f2b7d3784dd3a59f0ca11abe2 Mon Sep 17 00:00:00 2001
From: Samuel Lindemer <samuel.lindemer@gmail.com>
Date: Wed, 2 Jun 2021 16:39:52 +0200
Subject: [PATCH] Combine all the PMP logic into one FSM

---
 .../scala/vexriscv/plugin/PmpPlugin.scala     | 61 ++++++++++---------
 1 file changed, 31 insertions(+), 30 deletions(-)

diff --git a/src/main/scala/vexriscv/plugin/PmpPlugin.scala b/src/main/scala/vexriscv/plugin/PmpPlugin.scala
index 36626b1..1cebfe7 100644
--- a/src/main/scala/vexriscv/plugin/PmpPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/PmpPlugin.scala
@@ -160,7 +160,7 @@ class PmpPlugin(regions : Int, granularity : Int, ioRange : UInt => Bool) extend
           }
           when (pmpaddrCsr) {
             csrService.allowCsr()
-            csrService.readData() := pmpaddr.readAsync(pmpNcfg).asBits
+            csrService.readData() := pmpaddr(pmpNcfg).asBits
           }
         }
       }
@@ -173,28 +173,12 @@ class PmpPlugin(regions : Int, granularity : Int, ioRange : UInt => Bool) extend
             writeData_ := csrService.writeData()
             pmpNcfg_ := pmpNcfg
             pmpcfgN_ := pmpcfgN
-            pmpaddrCsr_ := pmpcfgCsr
-            pmpcfgCsr_ := pmpaddrCsr
+            pmpcfgCsr_ := pmpcfgCsr
+            pmpaddrCsr_ := pmpaddrCsr
           }
         }
       }
 
-      val writer = new Area {
-        when (pending) {
-          arbitration.haltItself := True
-          when (hazardFree & pmpaddrCsr_) {
-            val overwrite = writeData_.subdivideIn(8 bits)
-            for (i <- 0 until 4) {
-              when (~pmpcfg(pmpcfgN_ @@ U(i, 2 bits))(lBit)) {
-                pmpcfg(pmpcfgN_ @@ U(i, 2 bits)).assignFromBits(overwrite(i))
-              }
-            }
-          }
-        }
-        val locked = pmpcfg(pmpNcfg_)(lBit)
-        pmpaddr.write(pmpNcfg_, writeData_.asUInt, ~locked & pmpcfgCsr_ & pending & hazardFree)
-      }
-
       val controller = new StateMachine {
         val enable = RegInit(False)
         val counter = Reg(UInt(log2Up(regions) bits)) init(0)
@@ -205,21 +189,38 @@ class PmpPlugin(regions : Int, granularity : Int, ioRange : UInt => Bool) extend
             enable := False
             counter := 0
           }
-          onExit {
-            enable := True
-            arbitration.haltItself := True
-          }
           whenIsActive {
-            when (pending & hazardFree) {
-              when (pmpaddrCsr_) {
-                goto(stateCfg)
-              }.elsewhen (pmpcfgCsr_) {
-                goto(stateAddr)
+            when (pending) {
+              arbitration.haltItself := True
+              when (hazardFree) {
+                goto(stateWrite)
               }
             }
           }
         }
 
+        val stateWrite : State = new State {
+          onExit (enable := True)
+          whenIsActive {
+            arbitration.haltItself := True
+            when (pmpcfgCsr_) {
+              val overwrite = writeData_.subdivideIn(8 bits)
+              for (i <- 0 until 4) {
+                when (~pmpcfg(pmpcfgN_ @@ U(i, 2 bits))(lBit)) {
+                  pmpcfg(pmpcfgN_ @@ U(i, 2 bits)).assignFromBits(overwrite(i))
+                }
+              }
+              goto(stateCfg)
+            }
+            when (pmpaddrCsr_) {
+              when (~pmpcfg(pmpNcfg_)(lBit)) {
+                pmpaddr(pmpNcfg_) := writeData_.asUInt
+              }
+              goto(stateAddr)
+            }
+          }
+        }
+
         val stateCfg : State = new State {
           onEntry (counter := pmpcfgN_ @@ U(0, 2 bits))
           whenIsActive {
@@ -237,10 +238,10 @@ class PmpPlugin(regions : Int, granularity : Int, ioRange : UInt => Bool) extend
           whenIsActive (goto(stateIdle))
         }
 
-        when (pmpcfgCsr_) {
+        when (pmpaddrCsr_) {
           setter.io.addr := writeData_.asUInt
         } otherwise {
-          setter.io.addr := pmpaddr.readAsync(counter) 
+          setter.io.addr := pmpaddr(counter) 
         }
         
         when (enable & ~pmpcfg(counter)(lBit)) {