From 349d600182f5d64c86e65234fcb43bc9a8644cd2 Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Mon, 27 Mar 2017 00:33:34 +0200
Subject: [PATCH] Better readme cleaning

---
 README.md                                     | 67 +++++++++++++++++++
 .../scala/SpinalRiscv/Plugin/MachineCsr.scala |  2 -
 src/main/scala/SpinalRiscv/VexRiscv.scala     |  2 +-
 3 files changed, 68 insertions(+), 3 deletions(-)

diff --git a/README.md b/README.md
index 8c2aaa5..d5c30ea 100644
--- a/README.md
+++ b/README.md
@@ -17,8 +17,75 @@ The hardware description of this CPU is done by using an very software oriented
 - There is an automatic a tool which allow plugins to insert data in the pipeline at a given stage, and allow other plugins to read it in another stages through automatic pipelining.
 - There is an service system which provide a very dynamic framework. As instance, a plugin could provide an exception service which could then be used by others plugins to emit exceptions from the pipeline.
 
+
+## CPU instantiation 
+There is an example of instantiation of the CPU
+
+```scala
+//Define the cpu configuraiton
+val config = VexRiscvConfig(
+    pcWidth = 32
+)
+
+//Define the CSR configuration (riscv-privileged-v1.9.1)
+val csrConfig = MachineCsrConfig(
+    mvendorid      = 11,
+    marchid        = 22,
+    mimpid         = 33,
+    mhartid        = 0,
+    misaExtensionsInit = 66,
+    misaAccess     = CsrAccess.READ_WRITE,
+    mtvecAccess    = CsrAccess.READ_WRITE,
+    mtvecInit      = 0x00000020l,
+    mepcAccess     = CsrAccess.READ_WRITE,
+    mscratchGen    = true,
+    mcauseAccess   = CsrAccess.READ_WRITE,
+    mbadaddrAccess = CsrAccess.READ_WRITE,
+    mcycleAccess   = CsrAccess.READ_WRITE,
+    minstretAccess = CsrAccess.READ_WRITE,
+    ecallGen       = true,
+    wfiGen         = true
+)
+
+//Add plugins into the cpu configuration
+config.plugins ++= List(
+    new PcManagerSimplePlugin(0x00000000l, false),
+    new IBusSimplePlugin(
+        interfaceKeepData = true
+    ),
+    new DecoderSimplePlugin(
+        catchIllegalInstruction = true
+    ),
+    new RegFilePlugin(
+        regFileReadyKind = Plugin.SYNC,
+        zeroBoot = false
+    ),
+    new IntAluPlugin,
+    new SrcPlugin,
+    new FullBarrielShifterPlugin,
+    new DBusSimplePlugin(
+        catchUnalignedException = true
+    ),
+    new HazardSimplePlugin(true, true, true, true),
+    new MulPlugin,
+    new DivPlugin,
+    new MachineCsr(csrConfig),
+    new BranchPlugin(
+        earlyBranch = false,
+        catchUnalignedException = true,
+        prediction = DYNAMIC
+    )
+)
+
+//Instanciate the CPU
+val toplevel = new VexRiscv(config)
+```
+
+
 ## Plugin structure
 
+There is an example of an pseudo ALU plugin :
+
 ```scala
 
 //Define an signal name/type which could be used in the pipeline
diff --git a/src/main/scala/SpinalRiscv/Plugin/MachineCsr.scala b/src/main/scala/SpinalRiscv/Plugin/MachineCsr.scala
index de0140b..7d3fc8b 100644
--- a/src/main/scala/SpinalRiscv/Plugin/MachineCsr.scala
+++ b/src/main/scala/SpinalRiscv/Plugin/MachineCsr.scala
@@ -89,9 +89,7 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
   }
 
   object ENV_CTRL extends Stageable(EnvCtrlEnum())
-//  object EXCEPTION extends Stageable(Bool)
   object IS_CSR extends Stageable(Bool)
-//  object EXCEPTION_CAUSE extends Stageable(ExceptionCause())
 
   override def setup(pipeline: VexRiscv): Unit = {
     import pipeline.config._
diff --git a/src/main/scala/SpinalRiscv/VexRiscv.scala b/src/main/scala/SpinalRiscv/VexRiscv.scala
index 0c359ef..339bb04 100644
--- a/src/main/scala/SpinalRiscv/VexRiscv.scala
+++ b/src/main/scala/SpinalRiscv/VexRiscv.scala
@@ -7,7 +7,7 @@ import scala.collection.mutable.ArrayBuffer
 
 case class VexRiscvConfig(pcWidth : Int){
   val plugins = ArrayBuffer[Plugin[VexRiscv]]()
-  //TODO apply defaults to decoder
+
   //Default Stageables
   object BYPASSABLE_EXECUTE_STAGE   extends Stageable(Bool)
   object BYPASSABLE_MEMORY_STAGE   extends Stageable(Bool)