From 34e5cafb75142842dd8db7ed64d7d161ddbfd4ef Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 20 Dec 2021 09:38:02 +0100 Subject: [PATCH] Enable scala 2.13 compatibility --- .../scala/spinal/lib/eda/icestorm/IcestormFlow.scala | 2 ++ src/main/scala/vexriscv/VexRiscv.scala | 9 +++++---- src/main/scala/vexriscv/demo/Briey.scala | 2 +- src/main/scala/vexriscv/demo/Murax.scala | 5 +++-- 4 files changed, 11 insertions(+), 7 deletions(-) diff --git a/src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala b/src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala index b6ab7b5..6ef8d08 100644 --- a/src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala +++ b/src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala @@ -13,6 +13,8 @@ import spinal.lib.eda.bench.Report import scala.sys.process._ +import scala.collection.Seq + object IcestormFlow { def doCmd(cmd : Seq[String], path : String): String ={ println(cmd) diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala index 2bc647d..d3feda3 100644 --- a/src/main/scala/vexriscv/VexRiscv.scala +++ b/src/main/scala/vexriscv/VexRiscv.scala @@ -4,6 +4,7 @@ import vexriscv.plugin._ import spinal.core._ import scala.collection.mutable.ArrayBuffer +import scala.collection.Seq object VexRiscvConfig{ def apply(withMemoryStage : Boolean, withWriteBackStage : Boolean, plugins : Seq[Plugin[VexRiscv]]): VexRiscvConfig = { @@ -135,10 +136,10 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{ plugins ++= config.plugins //regression usage - val lastStageInstruction = CombInit(stages.last.input(config.INSTRUCTION)) keep() addAttribute (Verilator.public) - val lastStagePc = CombInit(stages.last.input(config.PC)) keep() addAttribute (Verilator.public) - val lastStageIsValid = CombInit(stages.last.arbitration.isValid) keep() addAttribute (Verilator.public) - val lastStageIsFiring = CombInit(stages.last.arbitration.isFiring) keep() addAttribute (Verilator.public) + val lastStageInstruction = CombInit(stages.last.input(config.INSTRUCTION)).keep().addAttribute (Verilator.public) + val lastStagePc = CombInit(stages.last.input(config.PC)).keep().addAttribute(Verilator.public) + val lastStageIsValid = CombInit(stages.last.arbitration.isValid).keep().addAttribute(Verilator.public) + val lastStageIsFiring = CombInit(stages.last.arbitration.isFiring).keep().addAttribute(Verilator.public) //Verilator perf decode.arbitration.removeIt.noBackendCombMerge diff --git a/src/main/scala/vexriscv/demo/Briey.scala b/src/main/scala/vexriscv/demo/Briey.scala index 701af7b..32e6d62 100644 --- a/src/main/scala/vexriscv/demo/Briey.scala +++ b/src/main/scala/vexriscv/demo/Briey.scala @@ -24,7 +24,7 @@ import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal} import spinal.lib.system.debugger.{JtagAxi4SharedDebugger, JtagBridge, SystemDebugger, SystemDebuggerConfig} import scala.collection.mutable.ArrayBuffer - +import scala.collection.Seq case class BrieyConfig(axiFrequency : HertzNumber, onChipRamSize : BigInt, diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 05c8e00..7c679a1 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -16,6 +16,7 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin} import spinal.lib.com.spi.ddr._ import spinal.lib.bus.simple._ import scala.collection.mutable.ArrayBuffer +import scala.collection.Seq /** * Created by PIC32F_USER on 28/07/2017. @@ -313,13 +314,13 @@ case class Murax(config : MuraxConfig) extends Component{ //******** Memory mappings ********* val apbDecoder = Apb3Decoder( master = apbBridge.io.apb, - slaves = apbMapping + slaves = apbMapping.toSeq ) val mainBusDecoder = new Area { val logic = new MuraxPipelinedMemoryBusDecoder( master = mainBusArbiter.io.masterBus, - specification = mainBusMapping, + specification = mainBusMapping.toSeq, pipelineMaster = pipelineMainBus ) }